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Process for Suppression of Anomalous Sub-Threshold Leakage

IP.com Disclosure Number: IPCOM000114092D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Au, W: AUTHOR [+3]

Abstract

A split deposition process for polysilicon gates is described that reduces anomalous sub-threshold leakage in self-aligned MOSFET devices. Ion-implantation channeling in MOSFET devices occurs when the source-drain dopant channels vertically along polysilicon grains in the gate to cause local regions within the MOSFET channel to be counter-doped (*). The result is an undesired sub-threshold drain-to-source leakage current. If the polysilicon gate is deposited in more than one layer, and an ultra-thin insulating material is grown between the layers, polysilicon grains from layer to layer are uncorrelated, and vertical channeling through the polysilicon gate is reduced substantially. The result is a reduction in sub-threshold leakage current.

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This is the abbreviated version, containing approximately 84% of the total text.

Process for Suppression of Anomalous Sub-Threshold Leakage

      A split deposition process for polysilicon gates is described
that reduces anomalous sub-threshold leakage in self-aligned MOSFET
devices.  Ion-implantation channeling in MOSFET devices occurs when
the source-drain dopant channels vertically along polysilicon grains
in the gate to cause local regions within the MOSFET channel to be
counter-doped (*).  The result is an undesired sub-threshold
drain-to-source leakage current.  If the polysilicon gate is
deposited in more than one layer, and an ultra-thin insulating
material is grown between the layers, polysilicon grains from layer
to layer are uncorrelated, and vertical channeling through the
polysilicon gate is reduced substantially.  The result is a reduction
in sub-threshold leakage current.

      Split deposition of the gate consists of (1) interrupting a
conventional deposition part way through the process, (2) allowing
the growth of an ultra-thin layer of material such as Si3N4 or SiO2,
then (3) resuming the polysilicon gate deposition.  The entire
process may be done in situ.  The gate deposition can be interrupted
more than once, and additional layers of insulating material are
grown during each interruption.  Polysilicon grains in the separate
gate layers remain uncorrelated even after 45 minutes of processing
at elevated temperatures.  The split deposition process yields better
definition of MOSFET channel length and reduced sub-thres...