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Integrated Device Electronics Conversion Cycle Determination Method

IP.com Disclosure Number: IPCOM000114102D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 209K

Publishing Venue

IBM

Related People

Haig, RB: AUTHOR [+2]

Abstract

Described is a method of determining the number of conversion cycles an Integrated Device Electronics (IDE) controller must run to communicate with a bus master, as used in Personal Computer (PC) network applications. The technique describes the control logic and timing charts for both prefetched and non-prefetched data transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Integrated Device Electronics Conversion Cycle Determination Method

      Described is a method of determining the number of conversion
cycles an Integrated Device Electronics (IDE) controller must run to
communicate with a bus master, as used in Personal Computer (PC)
network applications.  The technique describes the control logic and
timing charts for both prefetched and non-prefetched data transfers.

      Typically, when a cycle is started by a local bus master to an
IDE controller, the IDE controller may be required to convert the
cycle into multiple cycles for its IDE interface.  The IDE controller
must correctly determine the number of conversion cycles to run,
given the original local bytes.  Also, the IDE controller may be
prefetching data from an external IDE data port.  This can modify the
number of conversion cycles that the IDE controller would generate.
The IDE controller must correctly determine the number of conversion
cycles based on the original byte enables, prefetching or
non-prefetching of the data port, and the type of cycle run on the
IDE interface, such as an eight bit or a sixteen bit cycle.

      In prior art, the most common way of allowing multiple cycles
to the IDE bus was to force the local bus to regenerate the cycles
based on the byte size lines on the local bus.  However, this
required extra local bus cycles and interconnecting pins for the byte
size pins.  Also, some local buses did not have support for the byte
size lines requiring an alternative method.  Another prior art method
was to create a counter for the number of bytes required and to
subtract as the information was transferred.  When the counter
reached zero, the transfer was completed.  However, this required
extensive logic to create the counter and the subtraction logic.
Also, it did not cover the problem of prefetched data port
information, since the decrementing of the counter would have to
occur in less than one cycle if the data was available in the data
prefetch buffer.  As a result, the key aspect of the problem was to
allow the byte enables to be changed for non-prefetched accesses, but
only look and change the upper byte enables for the prefetched
accesses.

      The concept described herein provides a means of determining
the number of conversion cycles, for both prefetched data port
information and non-prefetched information, by breaking the problem
into two interlaced answers.  The first answer is for non-prefetched
accesses and the second answer is to handle the prefetched data port
accesses.  During non-prefetched accesses, the byte enables are
latched at the beginning of the local bus cycle.  Then, based on the
access of the IDE interface, each byte is reset after its data has
been transferred.  When all the bytes have been reset, the transfer
is complete.  There is no need for byte size pins, or requiring the
forcing of the local bus to regenerate the cycle.  Also, the reset
byte enables can be...