Browse Prior Art Database

Rx Channel Control for Aligning Data from a First-In-First-Out RAM

IP.com Disclosure Number: IPCOM000114120D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 301K

Publishing Venue

IBM

Related People

Johnson, MA: AUTHOR [+3]

Abstract

A typical Rx Channel requires the usage of a temporary storage RAM to eliminate problems with bus latency. Most applications store the information that has been received in data buffers in memory. The task of aligning data from a fixed First-In-First-Out (FIFO) RAM out onto a variable size bus requires several multi-input algorithms. Some of the required features involve: o moving data to variable sized data buffers starting and ending on any byte boundary from a 4-byte-wide RAM, o a data bus width of either one, two, or four bytes, and o a temporary holding register that buffers the RAM and feeds the data bus - the RxFIFO_Out_Buffer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Rx Channel Control for Aligning Data from a First-In-First-Out RAM

      A typical Rx Channel requires the usage of a temporary storage
RAM to eliminate problems with bus latency.  Most applications store
the information that has been received in data buffers in memory.
The task of aligning data from a fixed First-In-First-Out (FIFO) RAM
out onto a variable size bus requires several multi-input algorithms.
Some of the required features involve:
  o  moving data to variable sized data buffers starting and ending
on
      any byte boundary from a 4-byte-wide RAM,
  o  a data bus width of either one, two, or four bytes, and
  o  a temporary holding register that buffers the RAM and feeds the
      data bus - the RxFIFO_Out_Buffer.

      This disclosure describes the logic used to control the FIFO
RAM and its clocking logic, along with a description of the register
that buffers the RAM and feeds the data bus, and its clocking logic.

      This represents a string of frame bytes, A, B, C, D....  being
written out to the Rx_Data_Buffer in Micro Channel memory.

      This section describes the methods used to enable the
doubleword aligned RxFIFO to pass its frame data out the
Rx_Data_Buffers in Micro Channel* memory.  These data buffers may
start on any byte boundary and may be of any length, thus ending on
any byte boundary.  The parsing of the frame and aligning of the
Rx_Data_Buffers as well as lining up the end of the frame within the
data buffer is described in detail in this section.  The methodology
used herein requires no counters or registers to indicate what is
contained within the RxFIFO, all calculations and decisions are based
purely on the values of the output of the RxFIFO and its address
pointers.

The following terms are used in this description:
 A[1,0]    Rx_Data_Buffer Address bits 1,0 - the two least
significant
           Rx_Data_Buffer Address bits 1,0 - the two least
significant
           address bits of the Rx_Data_Buffer captured each time the
           Rx_Data_Buffer Address field is read from the Rx Buffer
           Descriptor and incremented upon each frame data transfer.
 A[1,0]    Latched Rx_Data_Buffer Address bits 1,0 - the two least
           significant address bits of the Rx_Data_Buffer captured
           each time the Rx_Data_Buffer Address field is read from
the
           Rx Buffer Descriptor.  These bits are used to determine
how
           the RxFIFO bytes are steered out onto the Micro Channel
           Data bus.
 L[1,0]    Rx_Data_Buffer Length bits 1,0 - the two least significant
           length bits of the Rx_Data_Buffer captured each time the
           Rx_Data_Buffer Length field is read from the Rx Buffer
           Descriptor and decremented upon each frame data transfer.
 &Lsterling.[1,0] Latched Rx_Data_Buffer Length bit...