Browse Prior Art Database

Design of Portable Library using Parameterized Cells

IP.com Disclosure Number: IPCOM000114128D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Atallah, F: AUTHOR [+4]

Abstract

A method for rapidly targeting a library of custom logic layouts to various foundry technologies is disclosed. This method enables the design of automated, portable and technology-independent design while reducing library development cycle time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Design of Portable Library using Parameterized Cells

      A method for rapidly targeting a library of custom logic
layouts to various foundry technologies is disclosed.  This method
enables the design of automated, portable and technology-independent
design while reducing library development cycle time.

      Since our primary design frame work is provided by Cadence
company, we looked at Cadence for a parameterized design that would
allow the design of portable and technology-independent libraries.

      An original technique was developed that utilized two Cadence
software capabilities: Parameterized Cells and the Structure
Compiler.  A design entry interface to the Structure Compiler was
written in SKILL, the Cadence database access/manipulation language,
which is similar to C.  This program accepts input from a graphic
layout cell in which the designer places instances of parameterized
cells that define devices and contacts.  Its output is a string
variable that is passed to the Structure Compiler and contains all
the instances in a design with their associated parameters, some of
which determine their eventual compacted placement.

      Parameterized cells are constructs that are instances of a
supermaster that is defined once by the designer.  Geometric
dimensions are related to variables whose value can be different in
each instance.  Cadence software allows these variables to be
extracted from a user-defined technology file.  Thus, the basic
device dimensions can be set to their minimum groundrule values.
When ground-rules change, a new technology file is loaded and the
changes propagate throughout the library.  To take advantage of these
changes in terms of increased density and to avoid groundrule
violations, the positions of devices in each circuit must be
adjusted.

      The Structure Compiler places instances in a design in a
geometric arrangement that the designer defines once in a template.
Each instance contains an alignment rectangle on a reserved layer.
These rectangles are abutted in the resulting layout.  Thus, by
controlling the dimensions of these alignment rectangles in each
instance uniquely...