Browse Prior Art Database

Access Logic for Main Memory

IP.com Disclosure Number: IPCOM000114132D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Koehler, T: AUTHOR [+3]

Abstract

A high-speed access logic for main memory is described. As shown in Fig. 1, the access logic is divided into a write array 10, a read array 20 and a storage controller (STC) 30. The access logic is connected to one or more DRAM or EPROM modules 40. The write array 10 and the read array 20 are connected to the Processing Unit (PU) bus 5.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Access Logic for Main Memory

      A high-speed access logic for main memory is described.  As
shown in Fig. 1, the access logic is divided into a write array 10, a
read array 20 and a storage controller (STC) 30.  The access logic is
connected to one or more DRAM or EPROM modules 40.  The write array
10 and the read array 20 are connected to the Processing Unit (PU)
bus 5.

      Fig. 2 shows a more detailed view of the access logic.  The
write array 10 comprises a plurality of First-In-First-Out (FIFO)
write address memories 100 and a plurality of FIFO write data
memories, all of whose reset inputs are activated on power-up, i.e.,
on connection of the supply voltage.  A flag EF indicates that the
write data memories 100 contain no stored data.  A signal on the
address strobe AS together with a read/write signal WR/RD starts a
write cycle to write data into the write array 10.  The valid
addresses and data appearing on the PU bus 5 are written within one
cycle into the write address memory 100 and into the write data
memory 110 respectively.  The value of the flag EF is now changed to
indicate that there is data in the write array 10 and the flag
signals to the storage controller 30 that it should read the values
out of the write data and write address memories 100, 110 and write
them into the memory modules 40.  If there is sufficient data and
address memories 100, 110, the PU bus 5 can be released for other
purposes within a short time.  The so-called "First Access Time" for
the memory modules 40 becomes negligible and it is not necessary to
incorporate extra wait cycles in the microcode even if very slow
memory modules 40 are used.

      The read array 20 similarly consists of a plurality of read
address FIFO memories 120 and read data FIFO memories 130.  On
power-up, the address of the first storage location in the memory
modules 40 to be read is passed to the read address memories 120.
The requested data are passed under the control of the storage
controller 30 from the memory modules 40 to the read data memories
130.  A line inc...