Browse Prior Art Database

Card Feedback Select Mechanism for Personal Computers

IP.com Disclosure Number: IPCOM000114133D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 148K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+3]

Abstract

Described is an architectural implementation to provide a Card Select Feedback (CSF) mechanism for Personal Computers (PCs). The implementation pertains to PCs, which employ a Peripheral Component Interconnect (PCI) bus, so that PCs can efficiently provide a CSF latch that is functionally equivalent to that employed in PCs equipped with a Micro Channel* (MC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Card Feedback Select Mechanism for Personal Computers

      Described is an architectural implementation to provide a Card
Select Feedback (CSF) mechanism for Personal Computers (PCs).  The
implementation pertains to PCs, which employ a Peripheral Component
Interconnect (PCI) bus, so that PCs can efficiently provide a CSF
latch that is functionally equivalent to that employed in PCs
equipped with a Micro Channel* (MC).

      Typically, PCs employing the MC utilize a CSF mechanism to
provide verification, to a bus master device, that any particular
access has been recognized by a target device.  This technique is
generally used by diagnostic software to verify that particular
Input/Output (I/O) devices are responding to commands from the
Central Processing Unit (CPU).

      The CSF mechanism requires an output from each MC slave
resource device to indicate that the given device has detected an
access to its specific resources.  The outputs of the various slaves
in a system are then logically OR'ed together at a central point and
then presented back to the MC devices by way of pin -SFDBKRTN and
into a latch.  The latch can be read at I/O address 91 (hex) by the
system master to determine whether or not one of the connected
resources has responded.

      The system master may then clear the CSF latch by writing to
I/O port 91 (hex), thereby making it available for further use.  Fig.
1 shows a block diagram of the relevant elements of the CSF
architecture.

      PCs that are designed with the PCI internal bus do not provide
for a similar readable latching mechanism.  Such a mechanism can be
provided by imposing a restriction that each PCI device dedicate an
output signal that would be equivalent to the above described I/O
port 91 (hex).  However, this solution burdens all PCI devices with
the requirement of adding an additional output signal.

      The concept described herein provides a means whereby the PCI
bus incorporates a mechanism to indicate that a device has responded
to a specific bus access.  This mechanism utilizes the DEVSEL# pin so
that a signal can be used to indicate that the driving device has
decoded its address as the target of the current access.  As an
input, it indicates whether any device on the bus has been selected.

      A timing signal is initiated that can be generated relative to
certain PCI signals and is gated with the DEVSEL# signal.  The output
of this timing gate is then presented to a latch that is logically
equivalent to the latch used in I/O port 91 (hex).  This latch is
then read, or written, in a manner equivalent to that used in MC
systems.

      Fig. 2 shows a block diagram of the relevant elements of the
PCI bus, MC system, CSF architecture.  Signal -SFDBKRTN already
connects to the PCI-MC bridge chip by virtue of its connection to the
MC.  Only a sing...