Browse Prior Art Database

Micro Channel Master State Machine Employing an Unknown Clock

IP.com Disclosure Number: IPCOM000114153D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 227K

Publishing Venue

IBM

Related People

Cohen, A: AUTHOR [+3]

Abstract

The most straight forward way to implement a Micro Channel* bus master, i.e., to generate the appropriate waveforms for the output signals and sample the input signals on time, is through a primary state machine. The different output signals would be driven at the appropriate states, in compliance with the Micro Channel timing specification. The input signals would be sampled in the appropriate states, according to their timing specifications.

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Micro Channel Master State Machine Employing an Unknown Clock

      The most straight forward way to implement a Micro Channel* bus
master, i.e., to generate the appropriate waveforms for the output
signals and sample the input signals on time, is through a primary
state machine.  The different output signals would be driven at the
appropriate states, in compliance with the Micro Channel timing
specification.   The input signals would be sampled in the
appropriate states, according to their timing specifications.

      As with all state machines, some type of clock signal is
required.  One possible solution would be to use a dedicated clock.
However, the requirement of a dedicated clock could increase
production cost (i.e., by requiring an oscillator, an extra pin,
etc.).

      Another solution would be to use a clock which already exists
in the system.  However, if the master is to function in various
systems with different clocks, another problem arises: Since the
timing specifications of the Micro channel Architecture are absolute
values, the master's primary state machine must be "tailored" to a
specific clock frequency.  Driving the state machine with a different
clock from the one it had been designed for may cause violations of
the Micro Channel timing specifications for output signals and a
failure to sample input signals on time.  A possible solution for
this problem is to design a different state machine for each
frequency, and some mechanism (e.g., a configuration register
programmed by the software) which would determine which state machine
to use for a given frequency.  However, this solution has two major
drawbacks:
  1.  The various frequencies must be known at the time of the design
      process.
  2.  The design will incur added complexity.
  3.  The frequency of the device may change on the fly due to system
      requirements.

Disclosed is a solution that does not suffer these drawbacks (Fig.
1).

      It is possible to design the state machine for a specific
frequency (Fmax), in such a way that it will function correctly,
i.e., within the timing specification of the Micro Channel, for any F
< Fmax.

      The Micro Channel timing specifications that are relevant to a
bus master may be categorized in the following manner:
  1.  Minimum values for output signals (e.g., T2: -CMD active from
      status active):
       If such a condition is met for Fmax, it will necessarily be
met
       for any F < Fmax.
  2.  Maximum values for input signals (e.g., T14R: -SFDBKRTN valid
      from address bus and M/-IO valid):
        From the master's point of view, this kind of timing
        specification is actually a minimum condition referring to
when
        it is safe to sample the input signal.  Thus, if such a
        condition is met for Fmax, it will necessarily be met for
        any F < Fmax.
  3.  Maximum values f...