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Dotted Emitter BiComplementary Metal Oxide Semiconductor

IP.com Disclosure Number: IPCOM000114155D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

A BiCMOS NAND is described which uses a dotted emitter circuit topology to reduce the effects of capacitive loading and adds NFET devices and resistors to prevent excessive reverse base-emitter voltages on the NPN devices.

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Dotted Emitter BiComplementary Metal Oxide Semiconductor

      A BiCMOS NAND is described which uses a dotted emitter circuit
topology to reduce the effects of capacitive loading and adds NFET
devices and resistors to prevent excessive reverse base-emitter
voltages
on the NPN devices.

      A simple dotted emitter BiCMOS NAND is shown in Fig. 1.  NPN
emitter followers Q0 and Q1 serve two functions.  First, they isolate
the output of the CMOS inverters from output 10.  Second, the dotted
emitters perform the required NAND function since both the base of Q0
and the base of Q1 must be low for output 10 to be low.  In this
simple form, the base-emitter junctions are subject to reverse-bias
voltages that may degrade or damage the NPN devices.  The reverse
bias occurs when output 10 is held high by one NPN while the base of
the other NPN is held low.  The NPN that has its base held low has a
reverse bias nearly equal to the supply voltage.

      Techniques for limiting reverse-bias voltages in dotted emitter
BiCMOS NAND circuits have been reported (*).  An improved technique
is shown in Fig. 2.  Additional NFET devices T10 and T11 assure that
the bases of Q0 and Q1 will go low only under the unique condition of
(A1) . (A0) = 1, which is the only NAND input combination which is
the only NAND input combination which yields a low output at terminal
10.  Since neither base can be pulled low while output 10 is high,
neither NPN base-emitter junction is ever subj...