Browse Prior Art Database

New Growable Register Array Concept Design using a L1, L2* Approach

IP.com Disclosure Number: IPCOM000114159D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 142K

Publishing Venue

IBM

Related People

Gabillard, B: AUTHOR [+2]

Abstract

This document disclose a new approach to design a Growable Register Array (GRA). This approach uses a LSSD scanning chain which consists of a plurality of L1 and L2* latches connected in series.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

New Growable Register Array Concept Design using a L1, L2* Approach

      This document disclose a new approach to design a Growable
Register Array (GRA).  This approach uses a LSSD scanning chain which
consists of a plurality of L1 and L2* latches connected in series.

      In the classical approach a memory cell used one L1 and one L2
latches.  That means a minimum of 11 transistors were required in a
memory cell.  All the memory cells were connected in series, and
scannable by the clocks A and B.

      In the disclosed approach, the memory cells are still connected
in series and scannable by clocks A and B. However, the first memory
cell in the LSSD chain only uses one L1 latch, and the second memory
cell only uses one L2* latch.  In other words, all the even memory
cells use one L1 latch, and all the odd memory cells use one L2*
latch.

      Consequently, a GRA memory cell, which required 15 transistors
with the classical approach, only needs 10 transistors with the
invention.  As an example, a GRA memory cell area has been reduced
from 350 um2  down to 240 um2.  The array area is thus reduced by
about 31%.

      The invention, can also be used for medium density SRAM which
usually used an ABIST.  Indeed, with small SRAM, says less than 20Kb,
the area impact of the ABIST is a severe limitation.  With the
present invention, the memory cell include 1 extra device and become
testable without the use of an ABIST.  The array area increasement
due to the 7D memory cell is less than the ABIST area which can thus
be saved by removing the ABIST.

      As an example, consider a SRAM designed in CMOS 5L.  A 6D
memory cell has an area of 65 um.  Using the same design rule, a 7D
memory cell has an area of 74 um.  Where the transistor sizes for the
6D and 7D memory cells are respectively:
  6 Devices memory cell
  -----------------------------
  NFET driver width: N1 = N2 = 2.3 um
  NFET access width: N3 = N4 = 1.4 um
  PFET load   width: P1 = P2 = 1.4 um
  7 Devices memory cell
  -----------------------------
  NFET driver width: N1 = 0.85 um,  N2 = 1.7 um
  NFET access width: N3 = 0.70 um,  N4 = 1.5 um
  PFET load   width: P1 = 0.70 um,  P2 = 1.4 um
  NFET scan   width: N5 = 2.75 um

      The 7D cell is not symetrical in order to insure correct read,
write and scan operation.  Furthermore this 7D cell is slower than
the 6D cell.

      The ABIST area is considered constant and equal to 0.7 mm2, and
the peripheral circuit area is the same for the 6D and 7D cell array,
and is 38% of a chip area using a 6D cell.  The following table give
the SRAM area and the gain area versus density when using the
classical approach or the disclosed invention.
---------------------------------------------------------------------
 | DENSITY | ARRAY area | Array area | CHIP area | CHIP area | GAIN
|
 |   Kb    |   6D cell  |   7D cell  |  6D cell  |  7D cell
|percent|
 |      ...