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Tx Channel Control for Aligning Data into a First-In-First-Out RAM

IP.com Disclosure Number: IPCOM000114179D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 228K

Publishing Venue

IBM

Related People

Johnson, MA: AUTHOR [+2]

Abstract

A typical Tx Channel requires the usage of a temporary storage RAM to eliminate problems with bus latency. Most applications have the information that needs to be transmitted stored in data buffers in memory. The task of aligning data from a variable size bus into a fixed First-In-First-Out (FIFO) RAM requires several multi-input algorithms. Some of the required features involve: o moving data from variable sized data buffers starting and ending on any byte boundary into a 4-byte-wide RAM, o a data bus width of either one, two, or four bytes, and o a temporary holding register that buffers the data bus and feeds the RAM - the TxFIFO_In_Buffer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

Tx Channel Control for Aligning Data into a First-In-First-Out RAM

      A typical Tx Channel requires the usage of a temporary storage
RAM to eliminate problems with bus latency.  Most applications have
the
information that needs to be transmitted stored in data buffers in
memory.  The task of aligning data from a variable size bus into a
fixed
First-In-First-Out (FIFO) RAM requires several multi-input
algorithms.
Some of the required features involve:
  o  moving data from variable sized data buffers starting and
      ending on any byte boundary into a 4-byte-wide RAM,
  o  a data bus width of either one, two, or four bytes, and
  o  a temporary holding register that buffers the data bus
      and feeds the RAM - the TxFIFO_In_Buffer.

      Described is the logic used to control the FIFO RAM and its
clocking logic, along with a description of the register that buffers
the data bus and feeds the RAM, and its clocking logic.

      This section describes the methods used to enable the
doubleword aligned TxFIFO to gets its frame data from the
Tx_Data-Buffers
in Micro Channel* memory.  These data buffers may start on any byte
boundary and may be of any length, thus ending on any byte boundary.
The
parsing of the frame and aligning of the Tx_Data_Buffers as well as
lining up the end of the frame within the TxFIFO is described in
detail
in this section.  The methodology used herein requires no counters or
registers to indicate what is contained within the RxFIFO, all
calculations and decisions are based purely on the values of the
output
of the RxFIFO and its address pointers.

      The following terms are used in this description:
  A(1,0)  Tx_Data_Buffer Address bits 1,0 - the two least
           significant address bits of the Tx_Data_Buffer.  These
           bits are captured before this value is incremented
           (Angstrom(1,0)).
  A(1,0)  Latched Tx_Data_Buffer Address bits 1,0 - the two least
           significant address bits of the Tx_Data_Buffer Address
           captured when the Tx_Data_Buffer is read from the Tx
           Frame Descriptor.
  L(1,0)  Tx_Data_Buffer Length bits 1,0 - the two least significant
           length bits of the Tx_Data_Buffer.  These bits are
captured
           before this value is decremented (?(1,0)).
  ?(1,0)  Latched Tx_Data-Buffer Length bits 1,0 - the two least
           significant address bits of the Tx_Data_Buffer Length
           captured when the Tx-Data-Buffer is read from the Tx Frame
           Descriptor.
  S(1,0)  Steer bits 1,0 - control how the data is steered into the
           the TxFIFO_In_Buffer.
 RL(1,0)  Running_Length bits 1,0 - used in successive calculations
           of the Steer bits.
  Throughout this disclosure, a line through a symbol is used to
   indicate a logical "NOT".

  ...