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Hardware Scheme for the Support of Checksum Calculations

IP.com Disclosure Number: IPCOM000114194D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Branstad, MW: AUTHOR [+5]

Abstract

A hardware scheme for the computation of Internet and International Standards Organization (ISO) TP-4 checksums is disclosed. A folded adder tree which converges on the correct checksum after 2 cycles is used. This tree structure is combined with a barrel shifter and a multiplexor structure to support odd byte alignment of the input byte stream.

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This is the abbreviated version, containing approximately 52% of the total text.

Hardware Scheme for the Support of Checksum Calculations

      A hardware scheme for the computation of Internet and
International Standards Organization (ISO) TP-4 checksums is
disclosed.  A folded adder tree which converges on the correct
checksum after 2 cycles is used.  This tree structure is combined
with a barrel shifter and a multiplexor structure to support odd byte
alignment of the input byte stream.

      A structure similar to the one in Fig. 1 is used to collect a
dataflow and produce the checksum.  The Transmission Control
Protocol/Internet Protocol (TCP/IP) checksum is a simple sum of
16-bit quantities with the carry-out folded back into the result.
The ISO-TP4 checksum is more complicated.  The data is modified such
that the 8-bit sum (with end-around-carry) is equal to zero.  It is
also modified such that if each 8-bit byte is added to an accumulator
with end-around-carry that is shifted by 1 bit before each addition,
the accumulator will equal zero (either X'00'  or X'FF').  This
hardware produces the partial products which allow the support of
Fletcher's checksum algorithm.  See (*).

      Byte Alignment Barrel Shifting Logic - Each time new data comes
from the input stream, the input latches advance once.  Depending on
the low order two bits of starting address, the barrel shifter
selects one of 4 alignments to supply 32 bits to the output.  If the
input was not active in the previous cycle, or this is the last cycle
and the count is not an even 32-bit aligned count, the appropriate
outputs of the barrel shifter are turned off (provide zeros on the
output.  This zero padding and zero "between cycle" value assists the
checksum logic.  The circuitry used is shown in Fig. 2.

      TCP/IP Checksum Calcula...