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Nonvolatile PMOSFET Array DRAM with Substrate Plate Trench Cell

IP.com Disclosure Number: IPCOM000114205D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Kitamura, K: AUTHOR

Abstract

Disclosed is a NVDRAM (nonvolatile DRAM) cell using Substrate Plate Trench (SPT) cell. Introducing nonvolatility into conventional DRAMs has large advantages in low end applications. Compaired with conventional FLASH EEPROM, it can fully utilize DRAM cuircuitry and high speed DRAM operation remains as before.

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Nonvolatile PMOSFET Array DRAM with Substrate Plate Trench Cell

      Disclosed is a NVDRAM (nonvolatile DRAM) cell using Substrate
Plate Trench (SPT) cell.  Introducing nonvolatility into conventional
DRAMs has large advantages in low end applications.  Compaired with
conventional FLASH EEPROM, it can fully utilize DRAM cuircuitry and
high speed DRAM operation remains as before.

      When power is turned off, DRAM cell information is transferred
into NVRAM cell which is directly connected to each DRAM cell.
Estimated cell area will be about 20 square microns which is two
times the present 4 Mbit DRAM, then it is 50% level of conventional
1Mb DRAM cell area and 40% level of 0.8 micron generation SRAM cell
area.

Figs. 1 and 2 show a Schematic Cross Section and Write/Erase
Mechnaism.