One Chip VME Extension for Instrumentation Interface Implemented in a High Density Erasable Programmable Logic Device
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-28
This invention is a VME extension for Instrumentation (VXI)/VME interface design (Figure). It supports slave register based A16/D16 and A24/D16 transfers. It also supports programmable interrupts. It provides control logic for the A24/D16 card side for a user application.
One Chip VME Extension for Instrumentation Interface
in a High Density Erasable Programmable Logic Device
invention is a VME extension for Instrumentation (VXI)/VME
interface design (Figure). It supports slave register based A16/D16
and A24/D16 transfers. It also supports programmable interrupts. It
provides control logic for the A24/D16 card side for a user
Standard Interface - VME is a standard interface
protocol that allows multiple instruments to be connected to a
computer bus. VXI has VME as a subset and extends the specification
to include added features necessary for instrumentation. VXI stands
for Vme eXtension for Instrumentation.
supports the register-based slave device
specification of VXI. This includes dynamic configuration (MODID
support), standard manufacturer and model code, plus the VME
specification. The chip also supports the interrupt specification.
It does not support the message based device specification, although
this device type may be included in the same system without the chip
o VXI interface, allows communication with VME/VXI bus
o Dynamic configuration support, A24/D16, A16/D16 support,
register-based device support
o Interrupt capability via programmable Interrupt levels
o A24/D16 space control lines - 2 strobes (high and low byte),
address strobe, read/write line, data bus control lines
Registers - The VXI specification defines a set of base
registers for all device types. The base register configuration for
Register Mapped devices includes:
o The Logical Address Register. This register holds the offset
address for A16 address space. This register is set to FF[h]at
power on and will be modified by the Resource Manager during
dynamic configuration. The logical address bits are compared
address bits A13 -- A6, a match is made when A15, A14 are both
A13 -- A6 match ULA7 -- ULA0 and the address modifiers AM5 --
are either 2D[h] or 29[h]. If a match is made the chip will
respond and provide DTACK. Since the chip cannot provide open
collector outputs, DTACK must be inverted off chip by an open
o The Identification Register. This register holds the device
class, address space, and manufacturer ID. The Manufacturer ID
is FB3[h] and the chip is register-based A16/A24. Therefore,
this registe is hard-wired to CFB3[h].
o The Device Type Register. The required memory "m" is derived
from the formula 256(a)*2(23-m). With m = 6, a = 0 the memory
space is 128 kBytes. The model code is BB3[h], therefore the
device type register contains 6BB3[h].
o The Control Register. This register has 3 mo...