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Optimum Wait Cycle Control for the Optional Read Only Memory Devices

IP.com Disclosure Number: IPCOM000114214D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 172K

Publishing Venue

IBM

Related People

Inamura, A: AUTHOR [+2]

Abstract

Disclosed is a technique and circuit for getting a optimum WAIT cycle for the access to each of the optional Read Only Memory (ROM) devices mounted in the micro processor system in accordance with its access time, by referring the identification data about its own optimum WAIT cycle initially stored in the ROS itself. In this system, one of several kinds of ROM devices having several access times is selectively mounted, or in a case no ROM device is mounted, on each of the optional ROM device mounting areas.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Optimum Wait Cycle Control for the Optional Read Only Memory Devices

      Disclosed is a technique and circuit for getting a optimum WAIT
cycle for the access to each of the optional Read Only Memory (ROM)
devices mounted in the micro processor system in accordance with its
access time, by referring the identification data about its own
optimum WAIT cycle initially stored in the ROS itself.  In this
system, one of several kinds of ROM devices having several access
times is selectively mounted, or in a case no ROM device is mounted,
on each of the optional ROM device mounting areas.

      Fig. 1 shows the functional block diagram that implements this
technique.  The block comprises of 2 sub-blocks enclosed by the
broken line frames; the WAIT CONTROL BLOCK (1) and the OPTIONAL ROM
BLOCK (2).

      The WAIT CONTROL BLOCK (1) has several 2-bit registers named
WAIT SETUP REG-A (3), WAIT SETUP REG-B (4),....  each of which
corresponds to one of the optional ROM mounting areas in the OPTIONAL
ROM BLOCK (2) respectively.  These 2-bit resisters can be written any
value by the MPU (5) and are set to (bit1,bit0)=(0,0) at the power on
reset sequence.  This block also has the address decoder (6) that
generates the chip select signals; CS-A (7), CS-B (8),....  for
accessing the optional ROM mounting areas.

      The OPTIONAL ROM BLOCK (2) has several optional ROM mounting
areas; the OPTROM AREA-A (9), the OPTROM AREA-B (10),....  .  As for
the OPTROM AREA-A (9), following three mounting cases are selectively
available.
  - No Mount ...................  (case-1)
  - ROM-A1 Mount ...............  (case-2)
  - ROM-A2 Mount ...............  (case-3)

      Where, the optimum WAIT cycle of ROM-A1 (11) and ROM-A2 (12) is
1 WAIT and 0 WAIT cycle respectively.  Each of the other optional ROM
mounting areas; O PTROM AREA-B (10),...  also has its own available
mounting cases respectively.

      The MPU (5) can access all the optional ROM areas directly by
using the traditional Strobe-Ack asynchronous hand-shake.  All the
data bus signals that are connected to the optional ROM mounting
areas are pulled up to Vcc with several K ohm resisters (30), so that
high level value is read when the MPU (5) reads an un-mounted area.

      As shown in Fig. 2, each optional ROM device has the
identification(ID) data (13) initially stored in the ROM device
itself in addition to its original data (14).  The ID data includes
some bits to show the optimum WAIT cycle of the ROM device itself
based on this MPU (5).  In Fig. 2, the one byte area on the lowest
address of each optional ROM device is assigned for the ID data (13),
and bit0 and bit1 of it are assigned for the optimum WAIT cycle of
the optional ROM device according to the following assignments.
           bit1   bit0        optimum WAIT cycle
            0      0              2 WAIT
            0      1    ...