Browse Prior Art Database

Signal Quality and Timing Verification Method for Digital Computer Systems

IP.com Disclosure Number: IPCOM000114221D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Derrick, JE: AUTHOR

Abstract

Described is a hardware implantation method for automatic verification of signal quality and timing criteria, as used in digital computer systems. The implementation involves an extension of DC scan registers, multiple time-delayed versions of the system clocks, and a functional testing procedure for exercising the logic over extended operating conditions. Also included is an extended use of the verification function.

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Signal Quality and Timing Verification Method for Digital Computer
Systems

      Described is a hardware implantation method for automatic
verification of signal quality and timing criteria, as used in
digital computer systems.  The implementation involves an  extension
of DC scan registers, multiple time-delayed versions of the system
clocks, and a functional testing procedure for exercising the logic
over extended operating conditions.  Also included is an extended use
of the verification function.

      In prior art, verification of signal quality and timing was
time consuming due to increased system complexity, operating
frequency, and package density.  The verification was typically
applicable only to DC levels of testing, as defined by the DC test
function (see (*)).

      The concept described herein specifies a functional hardware
description and methodology for an associated testing procedure that
allows automatic verification of signal timings for synchronous
systems.  The hardware is imbedded in the product and therefore can
be used during normal system operation to check for dynamic timing
faults.

Three fundamental components are used in the automatic AC testing
facility, as follows:
  1.  An extended implementation of the DC scan registers.
  2.  Multiple time-delay versions of the system clocks.
  3.  A functional test for exercising the logic over extended
       operating conditions.

For item 1, the following inputs and output are added to the DC scan
register:
  o  CLKsu - Clock with active edge tSU before the system clock
active
      edge.
  o  CLKhd - Clock with active edge tHD after the system clock active
      edge.
  o  ACfault - Values of signal latched by CLKsu and CLKhd XORed,
      Common Open-Collector output with other AC test cells.

      Fig. 1 shows a block diagram of the functional AC test cell.
Fig. 2 shows a block diagram of the clocking networks to support the
AC testability feature.  Fig. 3 shows the timing waveforms as
supplied by the multiple time-delayed system clocks.

      During the testing phase, each signal must be verified for
signal quality and sufficient timing margins. ...