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Browse Prior Art Database

Frequency Modulator for Low Power Digital Integrated Circuit Applications

IP.com Disclosure Number: IPCOM000114224D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Lin, S: AUTHOR [+2]

Abstract

Disclosed is a power saving strategy for digital integrated circuit applications, ranging from PC to main frames, by dynamically adjusting the clock frequency according to the system loading. Lower frequency is used if the system is not executing intensive jobs, hence reducing power consumptions. The design of the frequency modulator to implement this idea is also presented.

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This is the abbreviated version, containing approximately 47% of the total text.

Frequency Modulator for Low Power Digital Integrated Circuit Applications

      Disclosed is a power saving strategy for digital integrated
circuit applications, ranging from PC to main frames, by dynamically
adjusting the clock frequency according to the system loading.  Lower
frequency is used if the system is not executing intensive jobs,
hence reducing power consumptions.  The design of the frequency
modulator to implement this idea is also presented.

      Portable applications have shifted from conventional low
performance products such as calculators and wristwatches to high
throughput, computationally intensive products such as notebook
computers and personal digital assistants.  These new applications
require low power consumption mainly due to the restriction of the
limited life times of batteries and their limited cooling systems.

      With the advance of technology, the clock frequency of today's
digital systems has been increased to the range of hundreds of MHz,
which greatly increases the system maximum throughput.  However, not
very often a user will rely on this high throughput.  Most of time
the user will be just doing text editing, analyzing data, or sitting
there idle.  When performing these jobs, the system can afford to use
lower clock frequency and still satisfy the users.  Hence in this
invention, we propose dynamically adjusting the clock frequency
according to the system loading in order to save the average power
consumptions, roughly given by
                                f C V sup 2 ,
where f is the clock frequency, C is the total capacitive loading,
and V is the supply voltage (Vdd).  Therefore, if we can decrease the
clock frequency by N folds, we can save the power by N folds.  If the
system is executing computationally intensive jobs, then the maximum
frequency will be used.  Otherwise, the 1/2, 1/4, or 1/8 of the
maximum frequency will be used.  Assume that the system employs
two-phase clocking to avoid the race condition; therefore, if the
system correctly function at the frequency fit should correctly
function at f/2, f/4 and f/8 This argument is valid if the system
uses edge-triggered latches.  If the system uses single-phase
clocking, the race condition can still be avoided by keeping the duty
cycle the same, 1/(2f), for each divid frequency.  This division can
be extended to f/2 sup n as long as the system can still correctly
function at f/2 sup n, which depends on the rate of charge leakage in
the dynamic CMOS gates or the DRAM's of the system.

      This frequency adjustment is realized through a frequency
modulator, comprising a series of frequency dividers.  The dividers
can generate f/2, f/4 and f/8 frequencies, which along with the input
frequency f are selected by a 4-to-1 multiplexer giving the output
frequency.  The selection input to the multiplexer is provided by the
digital system and stored in a 4-bit register.  The frequenc...