Browse Prior Art Database

Address Space Visibility for a Multiple Bank Firmware Computer System

IP.com Disclosure Number: IPCOM000114254D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 161K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+3]

Abstract

Described is a firmware implementation to provide simultaneous visibility of FLASH memory banks, as used a Personal Computer (PC) system. The implementation provides a means whereby the amount of code required to be executed in a power-on bank is kept to a minimum.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Address Space Visibility for a Multiple Bank Firmware Computer System

      Described is a firmware implementation to provide simultaneous
visibility of FLASH memory banks, as used a Personal Computer (PC)
system.  The implementation provides a means whereby the amount of
code required to be executed in a power-on bank is kept to a minimum.

      In certain computer applications it is advantageous to have
multiple banks of permanent code storage, such as Read Only Memory
(ROM) devices, and to have only one bank active at any given time.
If these banks can contain different versions of the same basic code,
it is necessary to be able to select the most recent bank for
activation.  If these banks share an address space and only one bank
is to be active at a specific time, then the active bank cannot
directly interrogate the other banks.  This limits the bank selection
process.

      The concept described herein provides a means whereby both
banks of memory have simultaneous visibility so as to minimize the
amount of code required to be executed in the power-on bank.  In this
way changes to the power-on bank can be kept to an absolute minimum
enabling the power-on bank update procedure to be opened.

      Typically, a PC system has a variety of address space bank
subsystems.  The most common bank subsystem arrangement is the use of
the ROM and the shadow Random Access Memory (RAM).  The ROM subsystem
is used to store the Power-On Self Test (POST) and the Basic Input
Output System (BIOS).  The overall speed at which the ROM can be
utilized is normally much less than the overall speed at which the
system RAM is utilized.  To improve system performance, certain PCs
have hardware and software support used to remap the contents of ROM
into a section of system RAM, called shadow-RAM.  In this case, the
memory controller is programmed to place an equal amount of RAM,
typically 128 KB, into the same address space as the ROM, such as hex
E000 and hex F000 segments, where a segment is 64 KB.  A mode is then
entered, where ROM is in the read mode and the shadow-RAM is in the
write mode.  In this way the contents of the ROM can be transferred
into the higher performance shadow-RAM.  The memory controller is
then further programmed to read from the shadow-RAM thereby utilizing
POST and BIOS operations out of the higher performance shadow-RAM.

      Certain PCs extend the above arrangement to have two 128 KB ROM
banks along with the shadow-RAM.  When the system is first
powered-on, one of the ROM banks is active by default.  This default
ROM bank performs certain test and initialization functions.  Under
certain conditions, the default bank is required to copy the contents
of the second ROM bank into the shadow-RAM.  As a result, there are
three different banks which are all required to be accessed through
the same address space.  At this point, the default ROM band
initializes a certain amount of system RAM, such as t...