Browse Prior Art Database

Direct Memory Access Controller for DASD Array Controller

IP.com Disclosure Number: IPCOM000114293D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 6 page(s) / 181K

Publishing Venue

IBM

Related People

Kakihara, T: AUTHOR [+2]

Abstract

Described is a Direct Memory Access (DMA) controller which provides for an efficient data transfer of large and small DASD array reads and writes between a host system and multiple disk drives configured as a RAID 3 DASD array which appears as a single large fast DASD to the host system. Because the RAID 3 arrays read and write parity coded segmented data to N+P DASDs synchronously, the data rate increases by N*single DASD rate. Also, the physical block size increases by N*single DASD block size.

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Direct Memory Access Controller for DASD Array Controller

      Described is a Direct Memory Access (DMA) controller which
provides for an efficient data transfer of large and small DASD array
reads and writes between a host system and multiple disk drives
configured as a RAID 3 DASD array which appears as a single large
fast DASD to the host system.  Because the RAID 3 arrays read and
write parity coded segmented data to N+P DASDs synchronously, the
data rate increases by N*single DASD rate.  Also, the physical block
size increases by N*single DASD block size.

      The DMA controller is invented to achieve an efficient data
transfer between the host system and the RAID 3 array.  A concurrent
buffer memory access feature and a dynamic bank switching feature of
the disclosure improve the read/write performance especially in a
single DASD emulation mode, in which the logical block size of the
RAID 3 array must be same as the single DASD block length.  In the
single DASD emulation mode, without the concurrent access and the
dynamic switching features, writing a single block of new data to the
RAID 3 array requires three I/O operations (read-modify-write) as
shown on Fig. 1:
  1.  reading the N*single block size of old data from the array to a
       buffer memory
  2.  writing a single block of new data from the host over the
buffer
       memory used in step 1
  3.  writing the N*single block size of the partially updated data
to
       the array

      The similarity applies to a misaligned block write to the array
which also requires three I/O operations(read-modify-write).
Referring now to Fig. 2, the concurrent access feature of the
disclosure allows the host system to write new data to an array
buffer during reading old data from the array to an another array
buffer simultaneously and dual channel chain transfer with the
dynamic bank switch of the disclosure allows writing partially
updated data to the array continuously from the two separate buffers
with no additional overhead, thus the extra one I/O operation is
eliminated in the single DASD emulation mode.

      Embodiment of the Disclosure - One embodiment of the present
disclosure will now be described by way of example only, with
reference to the accompanying drawings, in which:
  Fig. 3 shows a block diagram illustration of a DMA controller
   including a microprocessor (MPU), a Switching Data Path (SDP)
logic,
   memories, one host port and five array DASD ports representing a
   preferred embodiment of the present disclosure.
  Fig. 4 shows a block diagram of the DMA Control Logic shown in Fig.
3.
  Fig. 5 shows a block diagram of the DMA Bus Multiplexer (MUX) shown
   in Fig. 3.

      Referring now to Fig. 3, there is seen a block diagram of a
DASD array controller incorporating the DMA controller architecture
of the present disclosure as an example of N = 4.  The array
controller includes a Host System Interface Lo...