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Semiconductor Mask, the Structure and its Fabrication Method

IP.com Disclosure Number: IPCOM000114311D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kimura, A: AUTHOR [+2]

Abstract

Disclosed is a mask made of semiconductor wafer, the structure and its fabrication process. In Si LSI processing, a metal mask with holes is used for evaporation of metals to form a terminal metal on the chip. The use of the same material for the mask with that of chips to be made, i.e., Si for Si wafer, GaAs for GaAs wafer, InSb for InSb wafer and etc., provides the exact matching of the coefficient of thermal expansion of the mask to that of the substrate wafer in process. The technique solves the problems such as, the need for dimensional offset to the metal mask and alignment error between the mask and wafer, which are serious as the wafer size is increased. In addition, the process disclosed can vary the slope of holes and enables to make both symmetric and asymmetric cross section.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Semiconductor Mask, the Structure and its Fabrication Method

      Disclosed is a mask made of semiconductor wafer, the structure
and its fabrication process.  In Si LSI processing, a metal mask with
holes is used for evaporation of metals to form a terminal metal on
the chip.  The use of the same material for the mask with that of
chips to be made, i.e., Si for Si wafer, GaAs for GaAs wafer, InSb
for InSb wafer and etc., provides the exact matching of the
coefficient of thermal expansion of the mask to that of the substrate
wafer in process.  The technique solves the problems such as, the
need for dimensional offset to the metal mask and alignment error
between the mask and wafer, which are serious as the wafer size is
increased.  In addition, the process disclosed can vary the slope of
holes and enables to make both symmetric and asymmetric cross
section.  It is a simple process and allows a lower grade of wafer as
the mask, which enables a substantial cost reduction in mask
manufacturing.

      Prior art describes an isotropic etching of two silicon wafers
and back-to-back lamination [*], which is a rather expensive process.
The process disclosed here employs sand blasting, which is not
limited to the use of single-crystal wafer.  Photo process with a
resist for a thick film, followed by sand blasting forms array of
holes in the substrate wafer.  Control of the resist thickness, time
for sand blasting, with a mask and or that of mirror image combined
with...