Browse Prior Art Database

Handling of an IEEE 1394 High Performance Serial Bus Reset

IP.com Disclosure Number: IPCOM000114313D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

McCrary, RE: AUTHOR [+4]

Abstract

Disclosed is a method for allowing a bus master, that must perform a valid access on its system bus once it has requested it, to perform a cycle, even when an asynchronous reset event has occurred. This problem is solved by saving the state of the machine when the reset occurs, thereby continuing the request, waiting for a bus access, performing a single "dummy" data transfer, discarding the data, and signaling the backend interface that the channel is ready to be started again.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Handling of an IEEE 1394 High Performance Serial Bus Reset

      Disclosed is a method for allowing a bus master, that must
perform a valid access on its system bus once it has requested it, to
perform a cycle, even when an asynchronous reset event has occurred.
This problem is solved by saving the state of the machine when the
reset occurs, thereby continuing the request, waiting for a bus
access, performing a single "dummy" data transfer, discarding the
data, and signaling the backend interface that the channel is ready
to be started again.

      This method can be generalized to handle any asynchronous reset
or stop type condition.  Since a 1394 bus reset can occur at any time
the bus master on the Peripheral Component Interconnect (PCI) bus may
be requesting the bus at that time.  Removing the request immediately
upon a reset from the Link-Phy interface may not be acceptable for
some arbitrators.  The method described is to sense the condition
(reset), save machine state, secure a bus access, perform one dummy
data transfer, return to reset state, and signal the backend
interface that the abort is completed.  Furthermore, the method
allows the backend interface to program up the Direct Memory Access
(DMA) channel immediately after reset, but it must wait to turn on
the "start" bit until the system bus interface indicates it is
acceptable to do so.

The steps are:
  1.  When an asynchronous reset/stop is sensed, a stop_master signal
       is generated until all channels are idle.  This stop_master
       signal is fed into the system bus protocol logic to insure
only
       one data phase occurs and the transaction is then termin...