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Input/Output Circuits Programmable in a Suspend Mode

IP.com Disclosure Number: IPCOM000114330D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Described are circuits providing device protection and programmability during the suspend mode operation of a system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Input/Output Circuits Programmable in a Suspend Mode

      Described are circuits providing device protection and
programmability during the suspend mode operation of a system.

      Present circuit chips containing a Central Processing Unit
(CPU) and associated controller units are usually designed to
minimize power consumption under the control of a built-in power
management unit.  In these complex chips, internal termination
networks for each signal pin may be included in addition to the
driver/receiver buffer circuitry.  The terminators may be provided by
an internal pull-up or pull-down resistor, or by a keeper circuit,
consisting of a weak driver that holds the pin at the last state
prior to the suspend mode operation.  Internal terminations are
typically provided for all input and bi-directional pins.

      During suspend mode operation, the state of each individual pin
is programmed by means of a power management control module on the
chip, with  input signals usually being disabled or enabled.  When an
input pin is disabled, the logic connected to the input is internally
electrically isolated, prohibiting signals from being recognized, and
the internal termination (pull-up or pull-down) on the pin is
tri-stated or disabled.  During the disabled mode, the output of the
receiver is kept at an inactive state.  On the other hand, an enabled
input buffer is internally programmable in an enable mode by means of
power management control, allowing the signal to be recognized
internally.

      Output and bi-directional signals are usually kept tri-stated,
active, or at a hold state.  When an output or input/output pin is
tri-stated, the output buffer (or the output driver of a
bi-directional signal) is floating; the logic connected to the input
receiver of a bi-directional signal is internally electrically
isolated; and the internal termination (pull-up or pull-down) on the
signal pin is tri-stated or disabled.  An active output buffer is
programmable active by means of power management control, as the
signal may change logical states while it continues to operate.
Bi-directional signals, or signals having an output which is to be
held, are held with internal keeper circuits at their last logical
levels before entering the suspend mode.

      Fig. 1 is a schematic diagram of a circuit implementing power
management control for a typical input (receiver) cell having an
input pad 12, including a programmable termination network.  A
suspend signal, +PMGMENT SUSPEND (HHIZ) is provided at input 14, and
a receiver inhibit signal, +RCVR INHIBIT is provided at input 16.
The output 17 from this circuit is provided as an input to a boundary
scan input cell and core logic.

      Advantages in circuit density and performance are accomplished
by fully integrating the control and termination circuitry with a
typical receiver circuit, within the area allocated for the I/O cell.
By integrating these devices with the rec...