Browse Prior Art Database

Method for Optimizing Changes to Clock Trees on Very Large Scale Integration Chips

IP.com Disclosure Number: IPCOM000114360D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Doyle, JJ: AUTHOR [+3]

Abstract

This invention applies to logic changes that are made to parallel-repowered clock trees after the original logic has been placed and wired.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Method for Optimizing Changes to Clock Trees on Very Large Scale
Integration Chips

      This invention applies to logic changes that are made to
parallel-repowered clock trees after the original logic has been
placed and wired.

      Described is a method that will automatically determine which
one of the equivalent clock copies is best able to drive each new
latch.

      The new latches are first placed in empty sockets, optimizing
the data flow without regard to clocks.  The clock tree is then
optimized using CLKOPT.  CLKOPT can be constrained to avoid swapping
any of the clock inputs of the old latches.  This avoids creating
lots of overflows in the wiring.  CLKOPT connects each new latch to
the nearest equivalent clock copy that can handle the load while
still being well-balanced.