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Calibration of Phase Locked Loop Single Shot Timing

IP.com Disclosure Number: IPCOM000114366D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Jaquette, GA: AUTHOR [+2]

Abstract

A method for calibrating the optimal single shot timing, or offset from nominal timing, is disclosed. This technique makes use of a programmable single-shot which allows optimizaiton of the single shot setting via bit error rate. Once the optimal Phase Locked Loop (PLL) single shot setting is determined via this calibration, the PLL can be run at a minimal error rate by use of this setting. This calibration can be performed at manufacture of a device employing the PLL and stored to some involatile memory in the drive for use as the single shot setting or as an input to a calculation which determines the single shot setting. In the case of magnetic or optical recording, this calibration could also be performed in the field in the case of heroic data recovery on an otherwise unrecoverable record or sector.

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Calibration of Phase Locked Loop Single Shot Timing

      A method for calibrating the optimal single shot timing, or
offset from nominal timing, is disclosed.  This technique makes use
of a programmable single-shot which allows optimizaiton of the single
shot setting via bit error rate.  Once the optimal Phase Locked Loop
(PLL) single shot setting is determined via this calibration, the PLL
can be run at a minimal error rate by use of this setting.  This
calibration can be performed at manufacture of a device employing the
PLL and stored to some involatile memory in the drive for use as the
single shot setting or as an input to a calculation which determines
the single shot setting.  In the case of magnetic or optical
recording, this calibration could also be performed in the field in
the case of heroic data recovery on an otherwise unrecoverable record
or sector.

      The Figure illustrates the concept involved.  Byte Error Rate
(BER) is plotted vs single-shot setting.  As can be seen, there is an
optimal setting which best centers the data histogram within the
detection window, minimizing the error rate.

      The pulse stream sent to the PLL can be characterized by their
deviation from ideal spacing, which should be integral numbers of
clock periods conforming to the Run Length Limited (RLL) code used.
Noise added in the recording/transmission and band limiting of the
channel used will cause these the detected pulses to vary from these
ideal positions.  Some variation is deterministic (such as
Inter-Symbol Interference (ISI) in a band-limited channel) and some
is stochastic (relatively random, actual statistics depend on the
noise spectrum).  In addition to ISI and additive noise, defects in
the recording media (or anomolous variation of, or coupling to, a
transmission channel) will cause pulse position variation.  Each of
these effects will statistically reduce the reliability with which
the pulsesa can be resynchronized.

      For best clock extraction and most faithful data
resynchronization, the PLL should center the expected data histogram
within the resynchronization window.  This will allow for the most
robust operation because a pulse must actually be perturbed by one
half of a clock period for it to be improperly resynchronized.  If
the ISI characteristics of the channel are symmetrical, this means
that nominal pulses (not suffering from ISI) should be in the center
of the PLL window.  If the PLL operates such that the pulses are not
centered within the resynchronization window, the margin for error is
reduced directly by the offset from it.  Typical resynchronization
PLLs use a single-shot to center the nominal data within the clock
window.  Variation from module to module, and module variation over
temperature and voltage excursions...