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Performance Tuning for the Power-On Self Test

IP.com Disclosure Number: IPCOM000114371D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

Disclosed is a method for improving the execution time for a Power-On Self Test (POST) firmware program. The primary performance gains are achieved by converting POST from a two-stage process to a one-stage process and reducing the amount of execution that occurs before POST transitions to Random Access Memory (RAM) from Read Only Memory (ROM).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

Performance Tuning for the Power-On Self Test

      Disclosed is a method for improving the execution time for a
Power-On Self Test (POST) firmware program.  The primary performance
gains are achieved by converting POST from a two-stage process to a
one-stage process and reducing the amount of execution that occurs
before POST transitions to Random Access Memory (RAM) from Read Only
Memory (ROM).

      The Table shows the general flow of the new tuned POST as it
compares to the extablished Initial Microcode Load (IML) type POST.

      Step 1 is early initialization such as checking the processor
after power-on.  Step 2 is where a performance improvement is
achieved.  Previously both the 128K bytes of Shadow-RAM and 640K
bytes of system RAM were tested by POST executing from ROM.
Executing from ROM, or a similar device, is slow.  In the tuned POST,
a small buffer of 64K is initialized and tested and the 128K
Shadow-RAM area is initialized and tested.  The small buffer (64K) is
needed for a code stub which is used to perform the ROM to Shadow-RAM
copy.  The firmware image is then transferred from ROM to Shadow-RAM
thus obtaining the execution speed advantage of Shadow-RAM.  The
remaining 576K of low RAM is then tested by POST which is now running
faster out of Shadow-RAM.

      Steps 3-6 then occur as shown in the table.  The IML of step 7
is not present in the tuned POST column since the dual-stage approach
of IML Post is replaced by a single-stage...