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Divide-By-2, 4, 8, 16 and 32 with Synchronized Outputs in a Phase Locked Loop

IP.com Disclosure Number: IPCOM000114385D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Nguyen, TC: AUTHOR [+3]

Abstract

This is a cascade of divide-by-2's with sychronized outputs of a Voltage Controlled Oscillator (VCO) frequency divided-by-2, 4, 8, 16 and 32 in a Phase-Locked Loop (PLL) that operates at a wide range of high frequencies.

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Divide-By-2, 4, 8, 16 and 32 with Synchronized Outputs in a Phase
Locked Loop

      This is a cascade of divide-by-2's with sychronized outputs of
a Voltage Controlled Oscillator (VCO) frequency divided-by-2, 4, 8,
16 and 32 in a Phase-Locked Loop (PLL) that operates at a wide range
of high frequencies.

      A cursory solution can be seen in Fig. 1.  Five master-slave D
Flip-Flops (DFF) are cascaded so that the first divided the VCO
frequency by 2 and this divided-by-2 frequency provides the input for
the next DFF and so on down the cascade until the VCO frequency is
finally divided-by-32.  Then a set of 5 master-slave DFFs gates the
outputs at the VCO frequency so the outputs are synchronized.  The
total delay of the 5 cascaded DFFs limits the range of this circuit.

      A more robust design that works over a wider range of
frequencies can be seen in Fig. 2.  The original 10 DFFs are still in
the circuit along with an additional 4 DFFs.  One of the requirements
is the sampling rate of the outputs of the DFFs that are
dividing-by-2 must be at least twice the frequency of the output of
the DFF.  This means the divide-by-4, 8, 16 and 32 are being  sampled
at a faster rate than necessary in the cursory solution.  The more
robust design uses half the VCO frequency to initially gate the
divided-by-4, 8, 16 and 32.  These 4 synchronized outputs and the VCO
frequency divided-by-2 output are then synchronized using the VCO
frequency.  Doing this creates 2...