Browse Prior Art Database

Memory Adapter Improvements for Personal Computers

IP.com Disclosure Number: IPCOM000114423D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 6 page(s) / 403K

Publishing Venue

IBM

Related People

Burge, BD: AUTHOR

Abstract

Described is an architectural implementation for a memory adapter that provides improvements in the areas of flexibility, capacity and compatibility for standard Personal Computers (PCs) and those equipped with a Micro Channel* (MC). The technique implements two distinct modes of operation; straddle mode and contiguous mode to provide improvements to existing memory adapters and is intended to be updatable for future memory technology.

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This is the abbreviated version, containing approximately 13% of the total text.

Memory Adapter Improvements for Personal Computers

      Described is an architectural implementation for a memory
adapter that provides improvements in the areas of flexibility,
capacity and compatibility for standard Personal Computers (PCs) and
those equipped with a Micro Channel* (MC).  The technique implements
two distinct modes of operation; straddle mode and contiguous mode to
provide improvements to existing memory adapters and is intended to
be updatable for future memory technology.

      In prior art, the certain memory adapters fell into two
categories, each of which had disadvantages.  For example, 0-6
megabyte (MB) and 0-8 MB memory adapters were designed to be
configured by means of a set configuration programs from reference
diskettes, but were limited to capacities of 6 and 8 MBs,
respectively.  Recently enhanced memory adapters had a capacity of up
to 32 MBs, but used a combination of a hard disk boot track
initialization programs and Read Only Memory (ROM) programs to
configure its memory.  Follow-on memory adapters used only ROM
programs, but had limited capacity.

      Typically, the prior art memory architecture was designed to
allow the flexibility of using the same options across the entire
product line.  The PC memory was architected with three distinct
interspersed address regions in which the system memory, such as
memory into which an operating system and application code may be
placed.  The three interspersed address regions involved non-system
memory, such as a buffer memory belonging to graphics, or other types
of adapters.

      System memory would exist at address ranges 0 to 640K-1, 1M
going toward 16M-1, and 16M going toward 4G-1.  Non-system memory
would exist from 640K to 1M-1, from 16M-1 going backward toward 1M,
and from 4G-1 going backward toward 16M.  The 0 to 640K-1 to 1M-1
address ranges for system and non-system memory were considered fixed
by the existing memory architecture.  It was assumed that neither
block of memory would expand outside either address range.  The 1M to
16M-1 and 16M to 4G-1 address ranges worked differently.  System
memory was architected to start at the lower end of each of these
address ranges and to go upward toward the high end, while non-system
memory was architected downward, or backward, toward the low end of
each of these address ranges.  Non-system memory was intended to take
precedence over system memory in each address range where they came
into conflict for the same address space.

      The overall intent was that the hardware with the non-system
memory would place that memory as high as possible in each of the two
address ranges.  Also, that the system would be configured starting
at the 1M address and going contiguously until the first block of
non-system memory was encountered, or until the end of available
system memory had been reached, whichever came first.  If non-system
memory had been encountered and there remained mor...