Browse Prior Art Database

Level Sensitive Scan Design Testable Self-Reseting Logic

IP.com Disclosure Number: IPCOM000114428D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

LeBlanc, JJ: AUTHOR [+4]

Abstract

Disclosed is a technique that allows Level Sensitive Scan Design (LSSD) legal testing of self-resetting circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Level Sensitive Scan Design Testable Self-Reseting Logic

      Disclosed is a technique that allows Level Sensitive Scan
Design (LSSD) legal testing of self-resetting circuits.

      To optimize performance, self-resetting circuit is chosen as
one of the primary technology in high-speed microprocessor design.
In order to take advantage of the existing LSSD test pattern
generation software, it is desirable to make self-resetting logic
circuit 'LSSD legal'.  This disclosure presents requirements to allow
LSSD legal testing of these components.

Fig. 1 illustrates the basic operation of 'self-resetting' logic
structures.

      Pulses (low to high) will be generated from the L2 latch of SRL
A beginning when the C2 clock becomes active.  True and complement
outputs of the L2 latch will be provided.  It is assumed that only
positive pulses (low-to-high) will only be generated (i.e., a pulse
on the true L2 output if SRL A is a '1' value or a pulse on the
complement L2 output if SRL A is at a '0' value).  This pulse will
travel through the self-resetting logic stages (S1 thru Sn).  After
the pulse propagates through a stage k+1 (i.e., stage k+1 is
'validated'), the previous stage, k, will be reset (precharged).  It
is also believed that the inputs to a given stage must be at (0,0)
before the stage can be safely precharged.  Stage S1 will be RESET
(PRECHARGED) when the outputs of S2 are validated (i.e.,
complementary)
AND when the true (T) and complement (C) inputs into S1 have been
RESET
(PRECHARGED) to (0,0).  Stage S2 will be RESET (PRECHARGED) by Stage
S3
and so forth.

      Fig. 2 illustrates how the last stage in a grouping is
precharged.  Stage n-1 will be RESET (PRECHARGED) when the...