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Cache Freeze Function in Level 2 Cache Controller

IP.com Disclosure Number: IPCOM000114430D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Furuta, M: AUTHOR [+3]

Abstract

This article describes a cache freeze function in Level 2 (L2) cache controller for enabling a personal computer system to keep the contents of L2 cache which should be flushed ordinarily when it enters and exits SMM (System Management Mode). Without the subject function, cache flushing is necessary to maintain cache coherency if the shadow memory region is overlaid on normal memory. In general, notebook PC system enters SMM frequently. Therefore, L2 cache had not been used efficiently, because cache is flushed and then reloaded again whenever the system enters and exits SMM. Such operation requires more power and performance penalty. With the function described bellow, the system with L2 cache can get more performance and save power consumption.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Cache Freeze Function in Level 2 Cache Controller

      This article describes a cache freeze function in Level 2 (L2)
cache controller for enabling a personal computer system to keep the
contents of L2 cache which should be flushed ordinarily when it
enters and exits SMM (System Management Mode).  Without the subject
function, cache flushing is necessary to maintain cache coherency if
the shadow memory region is overlaid on normal memory.  In general,
notebook PC system enters SMM frequently.  Therefore, L2 cache had
not been used efficiently, because cache is flushed and then reloaded
again whenever the system enters and exits SMM.  Such operation
requires more power and performance penalty.  With the function
described bellow, the system with L2 cache can get more performance
and save power consumption.

      The Figure shows the example of the SMRAM (shadow memory), and
the sequence of the subject function is processed as follows:
  1.  The system requests the CPU to enter SMM.
  2.  The CPU asserts the signal which indicates entering SMM.  And
       then, L2 cache is "frozen".  "Freeze" means prohibiting cache
       write operation.
  3.  -FLUSH signal is asserted to the CPU and L1 cache is flushed.
       But, L2 cache is NOT flushed.
  4.  During SMM, L1 cache in the CPU is cacheable but L2 cache is
       non-cacheable.
  5.  Cache invalidation is performed normally.  Cache invalidation
is
       also perfor...