Browse Prior Art Database

Pulse Width Modulation Signal Generator

IP.com Disclosure Number: IPCOM000114444D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

Mamiya, J: AUTHOR [+3]

Abstract

Disclosed here is a method of generating Pulse Width Modulation (PWM) signal, which is accurate, high resolution and suitable for digital control logic (i.e., microcomputer). The PWM signal is made from M-bit counter and L-bit variable Resistor and Capacitor (RC) delayer, so that the PWM signal duty can be adjusted by M+L bit resolution, which is smaller than the minimum counter clock.

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Pulse Width Modulation Signal Generator

      Disclosed here is a method of generating Pulse Width Modulation
(PWM) signal, which is accurate, high resolution and suitable for
digital control logic (i.e., microcomputer).  The PWM signal is made
from M-bit counter and L-bit variable Resistor and Capacitor (RC)
delayer, so that the PWM signal duty can be adjusted by M+L bit
resolution, which is smaller than the minimum counter clock.

      Fig. 1 shows the sample diagram of this method.  When N-bit
(N=M+L) input signal is applied to this circuit, the upper M-bit
signal will be loaded to M-bit counter, and the lower L-bit will be
loaded to L-bit variable RC delayer.

      M-bit counter runs by clock step after the M-bit input is
loaded, and in a while, Most Significant Bit (MSB) change occurs, to
change from Lo to Hi, or Hi to Lo.  The initial state of the MSB will
be reset by next load signal (Fig. 3 - Counter Output).  The length
of the period of MSB is Lo or Hi can be adjusted by clock step, and
the waveform of MSB becomes rectangular.

      Rectangle waveform of MSB is supplied to L-bit RC delayer.  In
Fig. 2, L-bit RC delayer is made from (L+1) resistors, (L) switches,
1 open corrector gate, 1 capacitor and 1 CMOS input gate.

      The L-bit input signal controls the switches to be ON or OFF.
The sum of the resistor values is L-bit variable and the delay time
of rise-up (or can be rise-down if the polarity of the logic is
inversely designed) of the signal is directly proportional to
Rtotal(ohm) x C(F) (Fig. 3 - RC delay).

      The rectangular signal from M-bit counter is entered into Open...