Browse Prior Art Database

MRC: Message Relaying Cascader

IP.com Disclosure Number: IPCOM000114450D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+5]

Abstract

Disclosed and shown in Figs. 2 and 3 is a mechanism designed for relaying messages in a network of adpaters interconnected by switches, with fast message routing capability and large adaptability to various physical network configurations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

MRC: Message Relaying Cascader

      Disclosed and shown in Figs. 2 and 3 is a mechanism designed
for relaying messages in a network of adpaters interconnected by
switches, with fast message routing capability and large adaptability
to various physical network configurations.

      As shown in Fig. 1, the basic hardware structure considered
here consists of several adapters interconnected by a switch.

      In such a structure, each adapter "Ad" includes a memory in
which messages are stored in queues.  The memory is accessed by:
  o  software running on a microprocessor;
  o  external network via the hardware "Network Interface";
  o  other adapters via the hardware "Switch Interface".

For each interface, there is a set of rcv and xmt queues in the
memory.

For the Switch Interface:
  o  The LOQs contain the messages to be transmitted to another
      adapter (1 queue per target);
  o  The MIQs contain the messages to be received from another
adapter
      (1 queue per origin).

The same arrangement applies for the Network Interface.

      The data movements between adapters are performed by the
hardware Switch Interface transferring messages.  For each message:
  o  The xmt adapter dequeues the message from LOQ and sends it to
the
      switch along with routing information;
  o  the switch routes the message to the specified target;
  o  the rcv adapter enqueues the message in MIQ.

      The final handling of data is performed by software which
analyzes the messages, processes them and send them to the final
destination via the Network Interface.

      The hardware structure is limited by the size of the switch.
For building a machine with a high number of adapters, several
switches are to be used as shown in Fig. 2.  The switches must be
interconnected to allow data transfers between any adapters.  The
Message Relaying Cascader is a specific adapter dedicated to switch
interconnection:

      The structure is then expandable to any network configuration
and to any number of adapters, switches and MRCs.

 ...