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High-Efficiency Bias Technique for Regulators and Amplifiers

IP.com Disclosure Number: IPCOM000114454D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Riggio Jr, SR: AUTHOR

Abstract

Described is the use of a Junction Field Effect Transistor (J-FET) in place of a resistor in a constant current bias technique applied in a low power DC-to-DC voltage regulator and in an audio amplifier.

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This is the abbreviated version, containing approximately 52% of the total text.

High-Efficiency Bias Technique for Regulators and Amplifiers

      Described is the use of a Junction Field Effect Transistor
(J-FET) in place of a resistor in a constant current bias technique
applied in a low power DC-to-DC voltage regulator and in an audio
amplifier.

      Traditional regulators and amplifiers are able to operate
adequately by using a resistor to place the active elements in the
active region.  However, this approach creates an efficiency problem
for a voltage regulator due to input voltage variations, and also
limits the output voltage swing in the audio amplifier.  It also
creates an efficiency problem for the audio amplifier and limits the
power delivered to the speaker.

      Fig. 1 is a schematic view of a traditional DC-to-DC voltage
regulator, in which an unregulated input voltage VIN and a reference
voltage VREF are used to provide a regulated output voltage VOUT.  A
biasing resistor 10 must be sized at the lowest value of an
unregulated input voltage VIN to provide enough bias current to
transistor 12 and voltage reference VREF.  Under this condition,
there is no efficiency problem.  However, when the unregulated input
voltage VIN increases, an excess of current flows in resistor 10 and
in the voltage reference VREF, causing a great deal more power to be
dissipated as heat and reducing the overall efficiency of the
regulator.

      Fig. 2 is a schematic view of a DC-to-DC voltage regulator
similar to the circuit of Fig. 1, except that a P-channel J-FET 14 is
put in place of resistor 10 (of Fig. 1).  In this way, the efficiency
problem is eliminated, since the P-channel J-FET 14 is connected to
have a gate-to-source voltage of zero, placing the device in a
constant-current mode.  Thus, the current flowing through J-FET 14 is
equal to the drain saturation current of the device.  This current
remains...