Browse Prior Art Database

486 L2 Write-through Cache Support in a Local Bus Multiprocessor System

IP.com Disclosure Number: IPCOM000114462D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Chan, FL: AUTHOR [+6]

Abstract

Disclosed is a mechanism that allows Local Bus master devices to operate in a 486 system that supports a look-aside L2 cache module (485TURBOCACHE). This cache is used to improve processor memory performance.

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486 L2 Write-through Cache Support in a Local Bus Multiprocessor
System

      Disclosed is a mechanism that allows Local Bus master devices
to operate in a 486 system that supports a look-aside L2 cache module
(485TURBOCACHE).  This cache is used to improve processor memory
performance.

      Fig. 1 shows a system implementation of an L2 cache without
local bus master devices.  The Intel 485TURBOCACHE module has a
BRDYO# signal that is connected to an AND gate.  This AND gate
combines all BRDY# signals from local bus devices.  The output of the
AND gate is connected to the 486 CPU_BRDY# signal.  This connection
allows the processor to terminate memory cycles from the L2 cache,
memory controller and other devices.

      Most local bus devices tri-state BRDY#, allowing many devices
to be attached to the same BRDY# signal.  When one device recognizes
a cycle to its region, that device will be the only one driving the
BRDY# signal.  The L2 cache does not tri-state this signal, therefore
an AND gate is needed to connect the cache BRDYO# signal with the
system BRDY# signal.

      Local bus master devices have a bi-directional BRDY# signal,
therefore this signal can be connected to the system BRDY#
connection.  Master devices cannot sample the L2 cache BRDYO# because
this signal is only connected to the AND gate input.  Therefore, the
cache must be disabled when a bus master owns the processor bus.
Fig. 2 shows a block diagram of a system with a look-as...