Browse Prior Art Database

Error Correcting Code Buffer for Single Chip Processor Store-in Cache

IP.com Disclosure Number: IPCOM000114465D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Irish, JD: AUTHOR

Abstract

A buffer that holds Error Correcting Code (ECC) check bits for modified data in a processor's on-chip store-in cache is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Error Correcting Code Buffer for Single Chip Processor Store-in Cache

      A buffer that holds Error Correcting Code (ECC) check bits for
modified data in a processor's on-chip store-in cache is disclosed.

      In order to allow modified data to be protected in a
processor's cache until it is written to main memory, a buffer is
added to hold ECC bits for the modified data.  The format of the
buffer would be:
            +---+--------------------------------+----------+
   Entry 1  | V | Cache Address of Modified Data | ECC bits |
            +---+--------------------------------+----------+
   Entry 2  |   |               "                |    "     |
            +---+--------------------------------+----------+
            |   |                                |          |
            |   |               .                |    .     |
            |   |               .                |    .     |
            |   |               .                |    .     |
            |   |                                |          |
            +---+--------------------------------+----------+
   Entry n  |   |               "                |    "     |
            +---+--------------------------------+----------+
   where V is a Valid bit

      The number of ECC Buffer entries implemented would be based on
a tradeoff between chip area and the limit imposed on the amount of
modified data that would be allowed to exist in the cache.  For the
example above, if 64 entries were provided, 3 percent of the cache
would be allowed to be different than Main Storage at any given time.

      The ECC Buffer entries may be organized either as fully
associative, meaning an entry for a particular piece of modified data
may exist in any entry of the ECC buffer, or Set associative, meaning
an entry is restricted, in where it can be placed, by some number of
the...