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Status Register Implementation which Mimics Atomic Bus Operations

IP.com Disclosure Number: IPCOM000114471D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bridges, JT: AUTHOR [+4]

Abstract

Most microprocessor-based systems contain status registers that are updated asynchronously to the program stream. The updating of status bits by the hardware is not usually related to the current instruction in execute. For example, timers or external interrupts can set status bits when the processor is not executing any instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Status Register Implementation which Mimics Atomic Bus Operations

      Most microprocessor-based systems contain status registers that
are updated asynchronously to the program stream.  The updating of
status bits by the hardware is not usually related to the current
instruction in execute.  For example, timers or external interrupts
can set status bits when the processor is not executing any
instruction.

      Code which manipulates a status register will typically read
the status register, determine which routines to dispatch based on
the bits set, and reset those bits which it intends to handle.

      To reset the bits to be handled, a read-modify-write procedure
is used.  Once the register is read and parsed, a mask is generated
that places zeroes in the bit positions of the status register to be
reset.  The mask is then written back to the status register.  The
bits that will be handled are cleared and the bits to which handling
is deferred remain set since ones are written back to their status
bit positions.

      A status register can also have bits SET by the code (as
opposed to the hardware) in order to emulate hardware that is not
available at the time of testing.  The register is read and logically
or'ed with a mask that turns on the bit of interest.  This new value
is written back to the status register.  This is also a
read-modify-write procedure.

      The problem with the read-modify-write procedure for PowerPC
and other architectures without an "atomic" operation in a single
cycle or a non-divisible way, is that between the read and write
operations new status bits can be set.  If a new status bit is (or
bits) set in this interval, the mask that is generated will place
zeroes on the new bits since they were not available at the time of
the read.  Writing this mask to the status register will reset the
new bit and ca...