Browse Prior Art Database

High Speed Tester Distributed Architecture

IP.com Disclosure Number: IPCOM000114476D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Clark, RA: AUTHOR [+2]

Abstract

Disclosed is an architecture that provides synchronized high speed stimulus data with low speed control and communication between the various Stimulus Units. The stimulus data can take the form of Control data, Address Data or Data Data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Tester Distributed Architecture

      Disclosed is an architecture that provides synchronized high
speed stimulus data with low speed control and communication between
the various Stimulus Units.  The stimulus data can take the form of
Control data, Address Data or Data Data.

      High speed Stimulus Data Generators distributed over several
circuit cards and connected through a backplane have a basic problem.
The design of the cards cause the data/address bus and communication
signals between the Stimulus Data Generators to take too long to
travel between cards because of delays in the gate and signal paths.

      The schematic in the Figure shows the distributed architecture.
The controlling section of the Test System, the Control Unit,
consists of a Main Control Ram, a Decode/Control circuit, a Next
Address Field counter and a Cycle Counter.  Instructions are executed
out of the Main Control Ram.  These instructions provide control
information for the Decode/Control circuit, the Cycle Count
associated with each instruction and also an address to be loaded
into the NAF counter when a jump is specified.

      Each Instruction consists of a number of cycles.  The Cycle
Counters for the Control Unit and for all the Stimulus Units are
always loaded at the start of each instruction with a count specified
by the instruction.  The counters are decremented for each cycle and
when a Cycle Count of zero (0) is reached, the Cycle Counters signal
their Address Counters and the Decode/Control to reload.  The control
information from the next instruction is loaded into the
Decode/Contr...