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Current Digital-Analog Converter of Improved Differential Nonlinearity

IP.com Disclosure Number: IPCOM000114495D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Bailey, JA: AUTHOR [+2]

Abstract

An improved Master-Slave (MS) current divider for a current digital analog converter (IDAC) is described. With this improvement, better binary scaling of all the currents is obtained because different current attenuation by the bipolar in the master and slave sections is avoided and all the bipolars have equal V sub CE bias. As a result, the Differential Nonlinearity (DN) of the IDAC is improved.

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Current Digital-Analog Converter of Improved Differential Nonlinearity

      An improved Master-Slave (MS) current divider for a current
digital analog converter (IDAC) is described.  With this improvement,
better binary scaling of all the currents is obtained because
different current attenuation by the bipolar in the master and slave
sections is avoided and all the bipolars have equal V sub CE bias.
As a result, the Differential Nonlinearity (DN) of the IDAC is
improved.

      An IDAC converts an N-bit digital input word to an output
analog current level, there being 2 sup N analog levels which form <2
sup N> - 1 current steps.  The Least-Significant Bit (LSB) is the
smallest nonzero analog current level and also equals a current step.
The LSB is the analog representation of the <1 sup st> power of 2;
while the Most-Significant Bit (MSB) is the analog representation of
the <<(N-1)>sup th> power of 2.  The maximum output current is the
Full-Scale (FS) current.  The Differential Nonlinearity (DN) is the
positive or negative deviation of a current step from its nominal
value of one LSB due to statistical variations of electrical
parameters.  If the DN is negative and larger than one LSB, the IDAC
output is not monotonic; that is, the slope of output current versus
bit number is negative.  In most IDAC applications, monotonicity is
required.

      Important circuits found in IDACs are a current divider and
binary switches as illustrated in Fig. 1 with a seven-bit IDAC.
Current dividers of the Master-Slave (M-S) type are commonly used to
obtain low DN with a low device count.  They are so named because
they are made up of two distinct sections known as the master and
slave sections.  In Fig. 1, the master section is made up of
resistors R40 through R71, forming a network known as an R-2R ladder,
and three cascode stages made up of single bipolars Q5A and Q5X, and
bipolar clusters Q6A-Q6B and Q7A-Q7B-Q7C-Q7D.  In what follows these
clusters will be respectively referred to by the single names of Q6
and Q7 and likewise for bipolar clusters found in the slave section.
The slave section is made up of clusters Q4, Q3, and Q2, and single
bipolars Q1A and Q1X.  The input current out of node BI is divided by
the R-2R ladder into four binary currents which correspond to the
MSB, the  <5 sup th> , and  the  <4 sup th>  power of 2.  The  <4 sup
th>  power current is duplicated; one copy flowing in resistor pair
R50-R51 and the other in resistor pair R40-R41.  The former current
copy and currents in resistor pairs R60-R61 and R70-R71 flow through
cascodes Q5A, Q6, and Q7, and switches S5, S6, and S7, respectively,
to output node 10 or the high-voltage power supply, VDD.  The latter
current copy flows through cascode Q5X and the slave section where it
is divided into binary currents corresponding to the  <3 sup rd> ,
<2 sup nd> ,  <1 sup st> , and  <0 sup th>  power-of-2, the last one
being the LSB current.  As in the m...