Browse Prior Art Database

Storage Access Mechanism for Vector Operands

IP.com Disclosure Number: IPCOM000114497D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Eberhard, RJ: AUTHOR [+3]

Abstract

Disclosed is an invention which improves the performance of vector operations in a multiprocessing environment by basing an operand's storage access on the operation's stride.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Storage Access Mechanism for Vector Operands

      Disclosed is an invention which improves the performance of
vector operations in a multiprocessing environment by basing an
operand's storage access on the operation's stride.

      Assumed for illustration of this invention but not necessarily
limiting to its scope is a storage subsystem comprising a primary
buffer cache (L1 Cache), a second level cache (L2 Cache) and a main
store (L3).  Connected to the primary buffer cache is a processing
unit which executes vector instructions and a single bi-directional
bus used for transferring both data and addresses to the second level
cache.  Also connecting the two caches is a command bus which is used
to exchange control information.

      Registers at both the L1 and L2 cache are provided to store a
vector instruction's address and stride.  Also provided is a vector
command queue which allows multiple microcoded vector requests for a
single instruction to be dispatched and queued with implicit storage
addressing.  The command queue also stores exceptions resulting from
a dispatched vector operation until the microcode's execution of the
instruction is synchronized with the storage unit.  A stride limit
register is provided in the L1 cache to determine when an element,
multiple elements, or a complete cache page should be requested from
the L2 cache.
  stride limit = (number of bytes/primary buffer cache page)/element
   size) - eln
  where eln = element number of first requested vector element of a
   primary buffer cache page

      For vector instructions which request elements from storage
using a stride greater than one, microcode initializes the stride
registers and issues to the L1 cache a storage request which
identifies the starting address of the first requested element.  The
control logic accesses the cache and delivers the first element to
the vector unit if the access results in a cache hit (cache
residency).  If a cache miss occurs, the L1 cache requests from the
L2 the cache page which stores the requested element, if the value
stored in the stride register is less than or equal to the value
stored in the stride limit register.  If the value stored in the
stride register exceeds the value stored in the stride limit
register, only the requested element is transferred from the L2.

      Subsequent element requests initiated by microcode for the same
vector instruction cause the L1 to compare the current element
address to the last element address.  If the storage access results
in an L1 miss and the difference between the last element address and
the current element address is an amount equivalent to the stride,
the L1 sends a command to the L2 that implicitly requests the next
element (no storage address is transferred to L2).  The L2 calculates
the storage address of the new request by incrementing the last
element address register by an amount stored in the stride register.
If the storage acce...