Browse Prior Art Database

Automatic Mode Adjustment

IP.com Disclosure Number: IPCOM000114510D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Sakakihara, M: AUTHOR [+2]

Abstract

In a device which provides a function of converting analog signals of Cathode Ray Tube (CRT) port (like PS/2 monitor interface) to digital signals and timings required for a digital display (like TFT/LCD panel), and which equips with Phase Lock Loop (PLL) to regenerate a same dot clock with a dot clock in PS/2 system by Hsync (Horizontal Synchronous pulse), frequency of the dot clock in the PS/2 system is not guaranteed as only one. For example, Video Graphics Array (VGA) has different two frequencies of the dot clocks according to display modes but the frequency of Hsync is the same. If the frequency of dot clock of PLL does not meet with the system one, Analog to Digital Converter (ADC) will fail to sample the analog video signals correctly.

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Automatic Mode Adjustment

      In a device which provides a function of converting analog
signals of Cathode Ray Tube (CRT) port (like PS/2 monitor interface)
to digital signals and timings required for a digital display (like
TFT/LCD panel), and which equips with Phase Lock Loop (PLL) to
regenerate a same dot clock with a dot clock in PS/2 system by Hsync
(Horizontal Synchronous pulse), frequency of the dot clock in the
PS/2 system is not guaranteed as only one.  For example, Video
Graphics Array (VGA) has different two frequencies of the dot clocks
according to display modes but the frequency of Hsync is the same.
If the frequency of dot clock of PLL does not meet with the system
one, Analog to Digital Converter (ADC) will fail to sample the analog
video signals correctly.

      This article describes the method to adjust the dot clock
frequency of PLL automatically to correspond with the frequency in
PS/2 system.

      The Figure shows the example of this method.  There are three
key portions in this Figure.  1st portion is to get Phase (#1 to #4),
2nd portion is to judge whether the frequency of dot clock of PLL
meets with the dot clock of the PS/2 system (Judge circuit #5), and
3rd is PLL (#6 to #7).  Here, "Phase" means a skew of analog video
signal against the dot clock of PLL.  And also it is assumed there
are only two different displayed modes.

      1st portion consists of Converter #1, Delay line #2,
D-Flip-Flop (D-FF) #3 and Binary conversion circuit #4.  Converter #1
is to convert the analog signal to the signal with enough level for

Delay line #2,  and the turn-on voltage is set to a little above
black level to get the rising edge of the video signal.  D...