Browse Prior Art Database

Automatic Sector Buffer Configuration

IP.com Disclosure Number: IPCOM000114560D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Kanamaru, A: AUTHOR [+4]

Abstract

Disclosed is a Hard Disk Drive (HDD) system which has a capability to cope with the different size of Random Access Memory (RAM). RAM in HDD is used for cache operation. This invention's HDD system can add a RAM without many changes of the micro code.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Automatic Sector Buffer Configuration

      Disclosed is a Hard Disk Drive (HDD) system which has a
capability to cope with the different size of Random Access Memory
(RAM).  RAM in HDD is used for cache operation.  This invention's HDD
system can add a RAM without many changes of the micro code.

      In current HDD systems, micro code must be changed in many
portions for changing the RAM size or adding new card assemblies.

      This invention provides a HDD system which can cope with more
than two different cache sizes.  Central Processing Unit (CPU) in HDD
systems includes not only RAM but also ROM (micro code), and ROM code
is printed in CPU pattern.  Therefore, current HDD system should have
two CPUs for handling two different sizes of cache.

      The new HDD system has two different versions.  One is one-RAM
type, and another is two-RAM type.  For handling these different
types, this new HDD system has a capability to access limited RAM
addresses depending on the number of RAM.  When in One-RAM (Mbyte)
HDD, 100000 h-11FFFEh can be accessed, and when in Two-RAM (2Mbyte)
type, 100000h-13FFFEh can be accessed.  The Figure shows the flow of
this new system.