Browse Prior Art Database

Microcontroller Interrupt Structure

IP.com Disclosure Number: IPCOM000114562D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 154K

Publishing Venue

IBM

Related People

Bubb, CE: AUTHOR [+3]

Abstract

Disclosed is a multiple level nested interrupt structure for a microcontroller. The various interrupt levels are used to handle hardware errors, instruction cache castins and errors, and normal work requests. A mechanism is provided to block interrupts while entering and exiting to allow critical information to be saved and restored. The work request interrupt is vectored to several different starting addresses to improve the performance by providing multiple entry points with different levels of register saving and restoring.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Microcontroller Interrupt Structure

      Disclosed is a multiple level nested interrupt structure for
a microcontroller.  The various interrupt levels are used to handle
hardware errors, instruction cache castins and errors, and normal
work requests.  A mechanism is provided to block interrupts while
entering and exiting to allow critical information to be saved and
restored.  The work request interrupt is vectored to several
different
starting addresses to improve the performance by providing multiple
entry points with different levels of register saving and restoring.

      The microcontroller described in this disclosure is part of a
larger computer system and has five nested interrupt levels.  The
interrupt levels are the external interrupt used to handle work
requests, the external error interrupt used to handle hardware errors
outside of the microcontroller, the instruction cache error interrupt
used to refetch instructions after parity errors are detected in the
instruction cache, the instruction cache miss interrupt used to fetch
instructions from main store, and the main store error interrupt used
to process errors passed to the microcontroller from the rest of the
system.  These interrupts are summarized in the table below.
  INTERRUPT NAME             PRIORITY        ENTRY ADDRESS
  Main store error           Highest             8010
  Instruction cache miss        .                8020
  Instruction cache error       .                8030
  External error                .                8040
  External                   Lowest          8050,60,70,80

      The highest priority interrupt is the main store error, and the
lowest priority is the external interrupt.  The microcontroller can
be interrupted from any priority level by a higher priority
interrupt.  When the higher priority interrupt completes, control is
returned to the lower priority interrupt.  When the microcontroller
is idle, it can be interrupted by any of the five interrupts.  This
design allows the external error interrupt to the interrupted by the
external error interrupt which in turn can be interrupted by the
instruction cache error interrupt, and so on.  As the interrupt
levels are processed and completed, control is returned back down the
lower level interrupt.

      An interrupt blocking mechanism allows the interrupt handling
code to save and restore certain key control registers when entering
and exiting interrupts and prevents other higher priority interrupts
from corrupting these control registers while they are being saved or
restored.  These control registers contain the instruction address of
the interrupted code and a few bits indicating key states of the
microcontroller (error states, condition codes, and interrupt enable
bits).  Each time an interrupt is taken, the block int...