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Browse Prior Art Database

Joint Test Action Group Sequence Error Detection

IP.com Disclosure Number: IPCOM000114565D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 6 page(s) / 227K

Publishing Venue

IBM

Related People

Angelotti, FW: AUTHOR [+2]

Abstract

A method for verifying state transitions in the IEEE 1149.1 Test Access Port (TAP) controller is disclosed. An enhanced protocol allows valid state transitions to take place and intercepts invalid state transitions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Joint Test Action Group Sequence Error Detection

      A method for verifying state transitions in the IEEE 1149.1
Test Access Port (TAP) controller is disclosed.  An enhanced protocol
allows valid state transitions to take place and intercepts invalid
state transitions.

      Joint Test Action Group (JTAG) (IEEE standard 1149.1) specifies
an edge-triggered clock (TCK).  Glitches can cause extra clocks to be
seen and expose the JTAG interface to improper operation that can
result in damage to components.  The solution to this problem must
not use more pins on components (such as complementary pair signals).

      The JTAG state machine on a part (also called a TAP controller)
uses the Test Mode Select (TMS) input strobed on the rising edge of
the TCK signal as its next-state control (Figure).  Any TMS value
accompanying a rising edge of TCK that causes a state transition is
translated into a pair of TMS values strobed by a pair of TCK rising
edges.  Compatibility with the standard is preserved by having the
device power-up using the state-transition mechanism prescribed by
the standard and using a JTAG instruction (a code transmitted over
the JTAG interface) to switch to the new method.

      All state transitions that are prescribed in the standard as
taking place on a TMS=1 when TCK rises condition are translated into
requiring a one on TMS with a rising edge of TCK, followed by a zero
(complementary value) on TMS with a second rising edge of TCK.  All
state transitions that are prescribed in the standard as taking place
on a TMS=0 when TCK rises condition are translated into requiring a
zero on TMS with a rising edge of TCK, followed by a one
(complementary
value) on TMS with a second rising edge of TCK.  The exception to
this
rule is the transition between Test-Logic-Reset and Run-Test/Idle
(explained later).  TMS values that cause the state machine to remain
in
the same state when TCK rises (see Test-Logic-Reset, Run-Test/Idle,
Shift-DR, Shift-IR, Pause-DR, and Pause-IR) do not use a second TCK
pulse with a complementary TMS value.

      When a sequence error is detected (two ones in a row or two
zeros in a row) the state machine resets to the Test-Logic-Reset
state and a flag inside the chip's JTAG controller is set to record
the error.  If the JTAG implementation has an error output signal, it
is activated.  Further TCK pulses are likely to create additional
sequence errors; this is good because JTAG control sequences are
likely to be programmed in large blocks at a tester.  If the sequence
error flag is set, the Shift-DR state of the JTAG state machine must
select the Bypass register, a one-bit shift register defined by the
standard.  This prevents modifying any data registers after a
sequence error occurs until it is reset by an instruction.

      Note that when the state machine exits Shift-DR or Shift-IR it
shifts the data in the Data Register (Shift-DR) or the Instruction
Register (Shift-I...