Browse Prior Art Database

High-Performance Multi-Port Frame Forwarding System

IP.com Disclosure Number: IPCOM000114570D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Bass, BM: AUTHOR [+6]

Abstract

Disclosed is a system for attaching several low-speed communication ports with one or more high-speed communication ports. The low-speed communication ports can be connected to the users of the system while the high-speed communication ports are usually connected to the network's backbone or high speed server. The High-Performance Multi-Port Frame Forwarding System describes the method used to attach these communication ports together and how to efficiently forward frames between these ports with little or no microprocessor overhead.

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High-Performance

Multi-Port

Frame Forwarding System

      Disclosed is a system for attaching several low-speed
communication ports with one or more high-speed communication ports.
The low-speed communication ports can be connected to the users of
the system while the high-speed communication ports are usually
connected to the network's backbone or high speed server.  The
High-Performance Multi-Port Frame Forwarding System describes the
method used to attach these communication ports together and how to
efficiently forward frames between these ports with little or no
microprocessor overhead.

      In the High-Performance Multi-Port Frame Forwarding System, the
low speed communication ports are directly attached to the internal
bus of the system through the appropriate interface hardware.  This
interface hardware communicates with the Memory and Buffer Manager
logic in order to store incoming communication frames in the
Dual-Port Frame Memory.

      The Memory and Buffer Manager logic is responsible for all
buffer management and queue management in the system.  The
microprocessor does not have to be involved in the data storage or
the forwarding of the communication frames from one port to the
other, thus relieving the microprocessor of programming overhead and
freeing it to run the necessary communication protocols.  The
communication ports directly request buffers from the Memory and
Buffer Manager as a frame is received and then pass additional
information to the Memory and Buffer Manager concerning the frame's
destination port after the frame has been completely stored in the
Dual-Port Frame Memory.  All buffer management and queue management
is handled by state machines in the Memory and Buffer Manager logic.

      Each communication port investigates the frame as it is
received to determine its destination.  Lookup tables and built-in
forwarding algorithms are incorporated in the interface logic to
determine where to send each incoming...