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Browse Prior Art Database

Low-Cost Electronic Over-Stress Prevention Network for Cards

IP.com Disclosure Number: IPCOM000114606D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

DeRemer, RL: AUTHOR [+3]

Abstract

Described is an Electronic Over-Stress Prevention Network (EOSPN) that protects Application Specific Integrated Circuit (ASIC) chip receivers (inputs) from noise spikes, is low cost, and requires very little board space to implement.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Low-Cost Electronic Over-Stress Prevention Network for Cards

      Described is an Electronic Over-Stress Prevention Network
(EOSPN) that protects Application Specific Integrated Circuit (ASIC)
chip receivers (inputs) from noise spikes, is low cost, and requires
very little board space to implement.

      Each circuit that receives a signal which may be susceptible to
fast transients is protected by the following circuit: a 3.0K ohm
series
resistor with a 0.01uF capacitor to ground (as shown in the Figure).

      The solution works well for fixed-level inputs and signals with
slow switching requirements.  The specific application was a
hot-pluggable cable which used several circuits to detect type and
presence.