Browse Prior Art Database

Mirror Imageable Random Access Memory Ball Grid Array

IP.com Disclosure Number: IPCOM000114609D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bartley, GK: AUTHOR [+3]

Abstract

A technique for a common Random Access Memory (RAM) Ball Grid Array (BGA) module and chip footprint design that is mirror-imageable is disclosed.

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Mirror Imageable Random Access Memory Ball Grid Array

A technique for a common Random Access Memory (RAM) Ball Grid Array (BGA) module and chip footprint design that is mirror-imageable is disclosed.

With a mirror-imaged module, it is now possible to mount the RAM BGA module on the topside of the card and connect it to the bottom RAM BGA module using a common thru via and a single net wire (Fig. 1). This improves the net topology by reducing the length of the stub off the main line wire and reduces the number of thru vias (reducing net capacitance). Improvements of these attributes improves the electrical performance of the nets. Having the capability to have one wire serve two RAM modules, the number card wires is reduced. This allows for a simpler raw card cross-section, which reduces the card cost.

By putting the RAM control signals down the center of the BGA substrate, these signals are automatically mirror-imageable (Fig. 2). Care must be taken for certain control signal (like Chip Select) that they mirror image to an unused (open) I/O to avoid Data Bus contention. While Fig. 2 shows a x16 organization, this design can be easily extended to other organizations (x4, x8, x9, x32, x36, etc).

The design of the RAM chip in the same manner as described for the substrate BGA. In IBM*, where A-wire chip designs puts the chip pads down the center of the chip, the same conversation applies as it did to the BGA substrate design, described above. With this design, it al...