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Very Large Scale Integration Testing Method using Multiple Compressors

IP.com Disclosure Number: IPCOM000114610D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Iwano, K: AUTHOR [+2]

Abstract

An algorithm is disclosed that efficiently checks whether Very Large Scale Integration (VLSI) circuits under testing are fault-free or not. The key ideas included in this disclosure are as follows: 1. The algorithm contains a number of compressors, whose outputs are compared with the correct reference data to decide whether there are any faults in the target VLSI or not. Fig. 1 is a block diagram which depicts how a number of compressors are coupled to a RAM under test. 2. Each compressor is a feedback shift register whose states represent a residue polynomial modulo a predetermined irreducible polynomial. An example of a compressor is shown in Fig. 2.

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Very Large Scale Integration Testing Method using Multiple Compressors

      An algorithm is disclosed that efficiently checks whether Very
Large Scale Integration (VLSI) circuits under testing are fault-free
or not.  The key ideas included in this disclosure are as follows:
  1.  The algorithm contains a number of compressors, whose outputs
are
       compared with the correct reference data to decide whether
there
       are any faults in the target VLSI or not.  Fig. 1 is a block
       diagram which depicts how a number of compressors are coupled
to
       a RAM under test.
  2.  Each compressor is a feedback shift register whose states
       represent a residue polynomial modulo a predetermined
irreducible
       polynomial.  An example of a compressor is shown in Fig. 2.

      The effect of (1) is to make the length of each compressor
short enough, while retaining the aliasing probability still small.
The effect of (2) is to make the aliasing probability of this system
theoretically analyzable, thus as well as practically controllable.
The combined effects of (1) and (2) are to make the transition time
of the state evolutions of compressors as small as possible, and to
make the overhead of the chip-area for the compressors as small as
possible.