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Browse Prior Art Database

Verifying Working L2

IP.com Disclosure Number: IPCOM000114624D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Peterson, JC: AUTHOR

Abstract

Disclosed is a method to verify the data on an L2 cache in a desktop PowerPC* system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Verifying Working L2

      Disclosed is a method to verify the data on an L2 cache in a
desktop PowerPC* system.

      In the desktop PowerPC system, the PCI Bridge and Memory
Controller buffer chip does not drive parity on the bus due to pin
limitations.  The (optional) L2 cache can be verified for correct
data only if parity is checked when it is supplied by the L2.

      The PowerPC processor interface consists of 64 data lines and
32 address lines.  Adding a bridge chip with memory and PCI interface
causes a problem with pin count if parity is added.  In order to
relieve the bridge chip of parity, external buffers are used that
route the memory parity on to the 601 processor bus (Figure).

      Since an optional L2 (store-in or write-through) will only
update its contents on memory cycles, correct parity will always be
stored in a working L2.  That is, when a PowerPC processor writes to
memory, it produces correct parity on the bus.  When it reads from
memory, the buffers provide the parity.

      Whenever the processor reads from the L2, the DPE_ (data parity
error) output is sampled.  However, since this signal will go active
on cycles that are not "hits" in the L2, such as a read from the I/O
bus, the bridge chip will selectively "screen" the DPE_ input from
the processor.  If the DPE_ asserted is from an L2 read hit, an error
condition/protocol will be asserted.  If the DPE_ asserted is caused
by any other access, the input is ignored...