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Method for Avoiding Register Invalidation

IP.com Disclosure Number: IPCOM000114627D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Robinson, JR: AUTHOR

Abstract

In a Microprocessor which performs out-of-order execution of instructions, it is common to provide a pool of registers which are "renamed", or assigned register numbers as instructions are decoded, and entered into the instruction queue. The total number of registers is greater than the architected register set so that at any time, the results of two or more instructions which modify the same architected register may be available simultaneously.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Method for Avoiding Register Invalidation

      In a Microprocessor which performs out-of-order execution of
instructions, it is common to provide a pool of registers which are
"renamed", or assigned register numbers as instructions are decoded,
and entered into the instruction queue.  The total number of
registers is greater than the architected register set so that at any
time, the results of two or more instructions which modify the same
architected register may be available simultaneously.

      In such a processor, it is necessary to indicate when a
register has been updated, and contains the result value of the
instruction to which the register has been assigned.  In this
invention, A validity indicator is contained in an array along with
the result data.  The register renaming control logic contains logic
which tracks the state of the validity indicator for each register
which is in the rename pool.

      When a register is assigned to receive the results of an
instruction, the current state of the indicator is inverted, and sent
to the execution unit which is to produce the result value for that
operation.  When a subsequent instruction references the contents of
this register, the execution unit(s) which will use the register
contents will be sent inverted validity indicator value.  The
execution unit which is updating the register value will write the
validity indicator with the value which was sent to it.  Since the
new value will cause the va...