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Browse Prior Art Database

Hybrid Surface Mount/Pin Grid Array Package

IP.com Disclosure Number: IPCOM000114639D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Peterson, JC: AUTHOR [+2]

Abstract

Disclosed is a hybrid surface mount package/pin array design which provides more pins for signal I/O on a given surface mount package than traditional designs. This design uses an array of pins inside the borders of the chip area for power and grounds, leaving all edge sites for signal I/O.

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Hybrid Surface Mount/Pin Grid Array Package

      Disclosed is a hybrid surface mount package/pin array design
which provides more pins for signal I/O on a given surface mount
package than traditional designs.  This design uses an array of pins
inside the borders of the chip area for power and grounds, leaving
all edge sites for signal I/O.

      Most surface mount packages must use about 20% of the I/O pins
to adequately distribute power to the chip.  Fig. 1 depicts a
Quad-Flat-Pack (QFP) with 240 pins.  About 192 pins are available for
signal I/O, and about 48 are used for power.

      The design disclosed here utilizes an array of pins under the
chip for power and grounds, and uses all edge sites for signal I/O,
as illustrated in Fig. 2.  The power and ground "pins" illustrated in
Fig. 2 may be actual array pins or a ball grid array.

      The power and grounds are located closer to the chip in this
design and are physically larger.  Consequently, fewer will be
required.

      There is no signal escape problem with voltage and ground pins,
since these typically connect to planes within the printed circuit
board.