Browse Prior Art Database

Exporting a Subset of Virtual Address Bits for L2 Support

IP.com Disclosure Number: IPCOM000114649D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Alexander, WP: AUTHOR [+2]

Abstract

Most systems which support a multi-level cache hierarchy perform the first-level (L1) cache access in parallel with the virtual-to-real address translation. Subsequent levels of cache and memory are indexed with bits from the physical address. Due to the effective random assignment of page frames by operating systems, adjacent virtual pages are scattered throughout real memory. Since the placement of data in real memory determines the placement of data in a physically-mapped L2 cache, this scattering of pages results in

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Exporting a Subset of Virtual Address Bits for L2 Support

      Most systems which support a multi-level cache hierarchy
perform the first-level (L1) cache access in parallel with the
virtual-to-real address translation.  Subsequent levels of cache and
memory are indexed with bits from the physical address.  Due to the
effective random assignment of page frames by operating systems,
adjacent virtual pages are scattered throughout real memory.  Since
the placement of data in real memory determines the placement of data
in a physically-mapped L2 cache, this scattering of pages results in

L2 cache conflicts which would not occur in a virtually-indexed L2
cache.  These additional conflicts degrade performance.  In addition,
the assignment of pages and the resulting conflicts vary from run to
run
causing fluctuations in program execution times.  These problems
appear
in all computer systems which include a physically-mapped L2 cache.

      This proposal would augment the physical address typically sent
to a L2-cache controller with a portion of the virtual address,
specifically those low-order bits of the virtual address which
distinguish pages.  The number of virtual address bits required
varies with L2 cache capacity and page size.  For example, a 1MB L2
cache in a system with 4KB pages would require exposing virtual
address bits VA12-VA19.  By indexing the L2 cache with these virtual
address bits along with a number (determined by the L2 cache line
size) of...