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Intersystem Channel Frame Reception State Machine

IP.com Disclosure Number: IPCOM000114654D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 109K

Publishing Venue

IBM

Related People

Gregg, TA: AUTHOR [+2]

Abstract

Disclosed is a hardware state machine used to process incoming frames in a serial communications link. The protocols on the links are optimized for the fastest possible processing of short messages while still accommodating much longer messages. The hardware state machine examines the received frame headers, makes the appropriate storage requests, and updates its state. If the frame is for a longer message, the state machine puts the frame header in a FIFO and interrupts the channel microprocessor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Intersystem Channel Frame Reception State Machine

      Disclosed is a hardware state machine used to process incoming
frames in a serial communications link.  The protocols on the links
are optimized for the fastest possible processing of short messages
while still accommodating much longer messages.  The hardware state
machine examines the received frame headers, makes the appropriate
storage requests, and updates its state.  If the frame is for a
longer message, the state machine puts the frame header in a FIFO and
interrupts the channel microprocessor.

      This disclosure relates to the message channel described in
(*).  In this message channel, the simplest exchange of frames
consists of a Message Command Block (MCB) sent by a sender channel at
one end of the link followed by a Message Response Block (MRB)
returned by a receiver channel at the other end of the link.
Slightly more complicated exchanges send DATA frames.  For a write
operation, the sender channel transmits a DATA frame after the MCB,
and for a read operation the receiver channel transmits a DATA frame
before the MRB.  It is the primary design goal of this channel to
perform the frame exchanges described above as quickly as possible.
This channel also allows exchanges of multiple DATA frames within a
single operation.  These operations are considerably more complicated
than the operations described earlier, and it is not a requirement to
perform them quickly.

      The frame reception state machine relieves the relatively slow
microprocessor from any involvement in processing frames received for
single or no DATA frame operations.  It maintains state information
and an enable bit for each of the two buffer sets.  Figs. 1 and 2 are
the state tables for the sender and receiver channels.  The first
column labeled EVENT describes the event on the inbound link.  For
example, the beginning of a DATA frame with the Additional data (A
bit) set to zero is shown in the first row.  The second column is the
current state and the third column is the next state.  The last
column indicates when the timeout timer should be stopped.  To
illustrate the state transitions, consider a single DATA frame read
operation as viewed by the sender channel.  The operation is started
by sending an MCB, and sending the MCB primes the state machine by
putting it in the IDLE state and setting the enable bit.  The
receiver responds to the MCB by sending a DATA frame followed by an
MRB.  Referring to Fig. 1, the DATA frame is received with the A bit
set to zero (DATA Start A bit = 0).  Since the state machine is in
the IDLE state, a storage request is made to start moving the data to
main store, and...